diff -Nur u-boot-1.1.4/board/atstk1000/atstk1000.c u-boot-1.1.4-avr32-20060621/board/atstk1000/atstk1000.c --- u-boot-1.1.4/board/atstk1000/atstk1000.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/atstk1000.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +static const struct sdram_info sdram = { + .phys_addr = CFG_SDRAM_BASE, + .row_bits = 11, + .col_bits = 8, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, +}; + +void board_init_memories(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->sdram_size = sdram_init(&sdram); +} + +void board_init_info(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_phy_id[0] = 0x10; + gd->bd->bi_phy_id[1] = 0x11; +} diff -Nur u-boot-1.1.4/board/atstk1000/atstk1002.c u-boot-1.1.4-avr32-20060621/board/atstk1000/atstk1002.c --- u-boot-1.1.4/board/atstk1000/atstk1002.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/atstk1002.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include + +#define USART0_PIOMASK ((1 << 8) | (1 << 9)) + +void board_init_pio(void) +{ + writel(USART0_PIOMASK, PIOA_BASE + 0x70); + writel(USART0_PIOMASK, PIOA_BASE + 0x04); +} diff -Nur u-boot-1.1.4/board/atstk1000/config.mk u-boot-1.1.4-avr32-20060621/board/atstk1000/config.mk --- u-boot-1.1.4/board/atstk1000/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/config.mk 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1 @@ +TEXT_BASE = 0x00000000 diff -Nur u-boot-1.1.4/board/atstk1000/eth.c u-boot-1.1.4-avr32-20060621/board/atstk1000/eth.c --- u-boot-1.1.4/board/atstk1000/eth.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/eth.c 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Ethernet initialization for the ATSTK1000 starterkit + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +extern int macb_eth_initialize(int id, unsigned int phy_addr); + +#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & CFG_CMD_NET) +void atstk1000_eth_initialize(bd_t *bi) +{ + int id = 0; + +#ifdef CFG_MACB0 + macb_eth_initialize(id++, bi->bi_phy_id[0]); +#endif +#ifdef CFG_MACB1 + macb_eth_initialize(id++, bi->bi_phy_id[1]); +#endif +} +#endif diff -Nur u-boot-1.1.4/board/atstk1000/flash.c u-boot-1.1.4-avr32-20060621/board/atstk1000/flash.c --- u-boot-1.1.4/board/atstk1000/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/flash.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CONFIG_ATSTK1000_EXT_FLASH +#include +#include +#include + +flash_info_t flash_info[1]; + +static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info) +{ + unsigned long flags; + + local_irq_save(flags); + + dcache_flush_unlocked(); + + writew(0xaa, flash + 0x555); + writew(0x55, flash + 0xaaa); + writew(0x90, flash + 0x555); + info->flash_id = readl(flash); + writew(0xff, flash); + + readw(flash); + + local_irq_restore(flags); +} + +unsigned long flash_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr; + unsigned int i; + + gd->bd->bi_flashstart = CFG_FLASH_BASE; + gd->bd->bi_flashsize = CFG_FLASH_SIZE; + gd->bd->bi_flashoffset = __edata_lma - _text; + + flash_info[0].size = CFG_FLASH_SIZE; + flash_info[0].sector_count = 135; + + flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]); + + for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) + flash_info[0].start[i] = addr; + for (; i < flash_info[0].sector_count; i++, addr += 0x10000) + flash_info[0].start[i] = addr; + + return CFG_FLASH_SIZE; +} + +void flash_print_info(flash_info_t *info) +{ + printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n", + info->flash_id >> 16, info->flash_id & 0xffff); + printf("Size: %ld MB in %d sectors\n", + info->size >> 10, info->sector_count); +} + +int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last) +{ + unsigned long flags; + unsigned long start_time; + uint16_t *fb, *sb; + unsigned int i; + int ret; + uint16_t status; + + if ((s_first < 0) || (s_first > s_last) + || (s_last >= info->sector_count)) { + puts("Error: first and/or last sector out of range\n"); + return ERR_INVAL; + } + + for (i = s_first; i < s_last; i++) + if (info->protect[i]) { + printf("Error: sector %d is protected\n", i); + return ERR_PROTECTED; + } + + fb = (uint16_t *)uncached(info->start[0]); + + dcache_flush_unlocked(); + + for (i = s_first; (i <= s_last) && !ctrlc(); i++) { + printf("Erasing sector %3d...", i); + + sb = (uint16_t *)uncached(info->start[i]); + + local_irq_save(flags); + + start_time = get_timer(0); + + /* Unlock sector */ + writew(0xaa, fb + 0x555); + writew(0x70, sb); + + /* Erase sector */ + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x80, fb + 0x555); + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x30, sb); + + /* Wait for completion */ + ret = ERR_OK; + do { + /* TODO: Timeout */ + status = readw(sb); + } while ((status != 0xffff) && !(status & 0x28)); + + writew(0xf0, fb); + + /* + * Make sure the command actually makes it to the bus + * before we re-enable interrupts. + */ + readw(fb); + + local_irq_restore(flags); + + if (status != 0xffff) { + printf("Flash erase error at address 0x%p: 0x%02x\n", + sb, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (ctrlc()) + printf("User interrupt!\n"); + + return ERR_OK; +} + +int __flashprog write_buff(flash_info_t *info, uchar *src, + ulong addr, ulong count) +{ + unsigned long flags; + uint16_t *base, *p, *s, *end; + uint16_t word, status; + int ret = ERR_OK; + + if (addr < info->start[0] + || (addr + count) > (info->start[0] + info->size) + || (addr + count) < addr) { + puts("Error: invalid address range\n"); + return ERR_INVAL; + } + + if (addr & 1 || count & 1 || (unsigned int)src & 1) { + puts("Error: misaligned source, destination or count\n"); + return ERR_ALIGN; + } + + base = (uint16_t *)uncached(info->start[0]); + end = (uint16_t *)uncached(addr + count); + + local_irq_save(flags); + + dcache_flush_unlocked(); + sync_write_buffer(); + + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; + p < end && !ctrlc(); p++, s++) { + word = *s; + + writew(0xaa, base + 0x555); + writew(0x55, base + 0xaaa); + writew(0xa0, base + 0x555); + writew(word, p); + + sync_write_buffer(); + + /* Wait for completion */ + do { + /* TODO: Timeout */ + status = readw(p); + } while ((status != word) && !(status & 0x28)); + + writew(0xf0, base); + readw(base); + + if (status != word) { + printf("Flash write error at address 0x%p: 0x%02x\n", + p, status); + ret = ERR_PROG_ERROR; + break; + } + } + + local_irq_restore(flags); + + return ret; +} + +#endif /* CONFIG_ATSTK1000_EXT_FLASH */ diff -Nur u-boot-1.1.4/board/atstk1000/Makefile u-boot-1.1.4-avr32-20060621/board/atstk1000/Makefile --- u-boot-1.1.4/board/atstk1000/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/Makefile 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,58 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +ifeq ($(SOC),ap7000) +DAUGHTERBOARD := atstk1002 +endif +ifndef DAUGHTERBOARD +DAUGHTERBOARD := unknown +endif + +LIB := lib$(BOARD).a + +SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c +OBJS := $(addsuffix .o,$(basename $(SRC))) + +.PHONY: all +all: .depend $(LIB) u-boot.lds + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +u-boot.lds: u-boot.lds.S ../../include/config.h + $(CPP) $(AFLAGS) -P -o $@ $< + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend u-boot.lds + +######################################################################### + +.depend: Makefile $(SRC) + $(CC) -M $(CPPFLAGS) $(SRC) > $@ + +-include .depend + +######################################################################### diff -Nur u-boot-1.1.4/board/atstk1000/u-boot.lds.S u-boot-1.1.4-avr32-20060621/board/atstk1000/u-boot.lds.S --- u-boot-1.1.4/board/atstk1000/u-boot.lds.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/u-boot.lds.S 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,86 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = CFG_FLASH_BASE; + _text = .; + .text : { + *(.text) + *(.text.exception) + } + + . = ALIGN(CFG_ICACHE_LINESZ); + __flashprog_start = .; + .flashprog : { + *(.flashprog) + } + . = ALIGN(CFG_ICACHE_LINESZ); + __flashprog_end = .; + + . = ALIGN(8); + .rodata : { + *(.rodata) + *(.rodata.*) + } + _etext = .; + + __data_lma = ALIGN(8); + . = CFG_INTRAM_BASE; + _data = .; + .data : AT(__data_lma) { + *(.data) + *(.data.*) + } + + . = ALIGN(8); + __got_start = .; + __got_lma = __data_lma + (__got_start - _data); + .got : AT(__got_lma) { + *(.got.plt) + *(.got) + } + __got_end = .; + + __u_boot_cmd_start = .; + __u_boot_cmd_lma = __got_lma + (__u_boot_cmd_start - __got_start); + .u_boot_cmd : AT(__u_boot_cmd_lma) { + *(.u_boot_cmd) + } + __u_boot_cmd_end = .; + + . = ALIGN(8); + _edata = .; + __edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start); + + .bss : { + *(.bss) + } + . = ALIGN(8); + _end = .; +} diff -Nur u-boot-1.1.4/board/omap730p2/Makefile u-boot-1.1.4-avr32-20060621/board/omap730p2/Makefile --- u-boot-1.1.4/board/omap730p2/Makefile 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/omap730p2/Makefile 1970-01-01 01:00:00.000000000 +0100 @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := omap730p2.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff -Nur u-boot-1.1.4/common/cmd_bootm.c u-boot-1.1.4-avr32-20060621/common/cmd_bootm.c --- u-boot-1.1.4/common/cmd_bootm.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/common/cmd_bootm.c 2006-06-21 11:58:22.000000000 +0200 @@ -250,6 +250,8 @@ if (hdr->ih_arch != IH_CPU_M68K) #elif defined(__microblaze__) if (hdr->ih_arch != IH_CPU_MICROBLAZE) +#elif defined(__avr32__) + if (hdr->ih_arch != IH_CPU_AVR32) #elif defined(__nios2__) if (hdr->ih_arch != IH_CPU_NIOS2) #else @@ -1243,6 +1245,7 @@ case IH_CPU_MICROBLAZE: arch = "Microblaze"; break; case IH_CPU_NIOS: arch = "Nios"; break; case IH_CPU_NIOS2: arch = "Nios-II"; break; + case IH_CPU_AVR32: arch = "AVR32"; break; default: arch = "Unknown Architecture"; break; } diff -Nur u-boot-1.1.4/config.mk u-boot-1.1.4-avr32-20060621/config.mk --- u-boot-1.1.4/config.mk 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/config.mk 2006-06-21 11:58:26.000000000 +0200 @@ -139,10 +139,10 @@ endif endif -AFLAGS_DEBUG := -Wa,-gstabs +AFLAGS_DEBUG := -Wa,-g AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) -LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +LDFLAGS += -Bstatic -T $(LDSCRIPT) $(PLATFORM_LDFLAGS) # Location of a usable BFD library, where we define "usable" as # "built for ${HOST}, supports ${TARGET}". Sensible values are diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/ap7000/devices.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/devices.c --- u-boot-1.1.4/cpu/at32ap7xxx/ap7000/devices.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/devices.c 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,448 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +#include "../sm.h" + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +const struct clock_domain chip_clock[] = { + [CLOCK_CPU] = { + .reg = SM_PM_CPU_MASK, + .id = CLOCK_CPU, + .bridge = NO_DEVICE, + }, + [CLOCK_AHB] = { + .reg = SM_PM_AHB_MASK, + .id = CLOCK_AHB, + .bridge = NO_DEVICE, + }, + [CLOCK_APBA] = { + .reg = SM_PM_APBA_MASK, + .id = CLOCK_APBA, + .bridge = DEVICE_APBA_BRIDGE, + }, + [CLOCK_APBB] = { + .reg = SM_PM_APBB_MASK, + .id = CLOCK_APBB, + .bridge = DEVICE_APBB_BRIDGE, + }, +}; + +static const struct resource hebi_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 0 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 13 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 14 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 }, + }, + }, +}; +static const struct resource apba_bridge_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 1 }, + } + }, { + .type = RESOURCE_CLOCK, + .u = { + /* AHB-AHB Bridge */ + .clock = { CLOCK_AHB, 4 }, + }, + }, +}; +static const struct resource apbb_bridge_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 2 }, + }, + }, +}; +static const struct resource hramc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 3 }, + }, + }, +}; +static const struct resource pioa_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 10 }, + }, + }, +}; +static const struct resource piob_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 11 }, + }, + }, +}; +static const struct resource pioc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 12 }, + }, + }, +}; +static const struct resource piod_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 13 }, + }, + }, +}; +static const struct resource pioe_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 14 }, + }, + }, +}; +static const struct resource sm_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 0 }, + }, + }, +}; +static const struct resource intc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 1 }, + }, + }, +}; +static const struct resource hmatrix_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 2 }, + }, + }, +}; +#if defined(CFG_HPDC) +static const struct resource hpdc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 16 }, + }, + }, +}; +#endif +#if defined(CFG_MACB0) +static const struct resource macb0_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 8 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 6 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 }, + }, + }, +}; +#endif +#if defined(CFG_MACB1) +static const struct resource macb1_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 9 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 7 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 }, + }, + }, +}; +#endif +#if defined(CFG_LCDC) +static const struct resource lcdc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 7 }, + }, + }, +}; +#endif +#if defined(CFG_USART0) +static const struct resource usart0_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 3 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 }, + }, + }, +}; +#endif +#if defined(CFG_USART1) +static const struct resource usart1_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 4 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 }, + }, + }, +}; +#endif +#if defined(CFG_USART2) +static const struct resource usart2_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 5 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 }, + }, + }, +}; +#endif +#if defined(CFG_USART3) +static const struct resource usart3_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 6 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 }, + }, + }, +}; +#endif +#if defined(CFG_MMCI) +static const struct resource mmci_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 9 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 }, + }, + }, +}; +#endif +#if defined(CFG_DMAC) +static const struct resource dmac_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 10 }, + }, + }, +}; +#endif + +const struct device chip_device[] = { + [DEVICE_HEBI] = { + .regs = (void *)HSMC_BASE, + .nr_resources = ARRAY_SIZE(hebi_resource), + .resource = hebi_resource, + }, + [DEVICE_APBA_BRIDGE] = { + .nr_resources = ARRAY_SIZE(apba_bridge_resource), + .resource = apba_bridge_resource, + }, + [DEVICE_APBB_BRIDGE] = { + .nr_resources = ARRAY_SIZE(apbb_bridge_resource), + .resource = apbb_bridge_resource, + }, + [DEVICE_HRAMC] = { + .nr_resources = ARRAY_SIZE(hramc_resource), + .resource = hramc_resource, + }, + [DEVICE_PIOA] = { + .regs = (void *)PIOA_BASE, + .nr_resources = ARRAY_SIZE(pioa_resource), + .resource = pioa_resource, + }, + [DEVICE_PIOB] = { + .regs = (void *)PIOB_BASE, + .nr_resources = ARRAY_SIZE(piob_resource), + .resource = piob_resource, + }, + [DEVICE_PIOC] = { + .regs = (void *)PIOC_BASE, + .nr_resources = ARRAY_SIZE(pioc_resource), + .resource = pioc_resource, + }, + [DEVICE_PIOD] = { + .regs = (void *)PIOD_BASE, + .nr_resources = ARRAY_SIZE(piod_resource), + .resource = piod_resource, + }, + [DEVICE_PIOE] = { + .regs = (void *)PIOE_BASE, + .nr_resources = ARRAY_SIZE(pioe_resource), + .resource = pioe_resource, + }, + [DEVICE_SM] = { + .regs = (void *)SM_BASE, + .nr_resources = ARRAY_SIZE(sm_resource), + .resource = sm_resource, + }, + [DEVICE_INTC] = { + .regs = (void *)INTC_BASE, + .nr_resources = ARRAY_SIZE(intc_resource), + .resource = intc_resource, + }, + [DEVICE_HMATRIX] = { + .regs = (void *)HMATRIX_BASE, + .nr_resources = ARRAY_SIZE(hmatrix_resource), + .resource = hmatrix_resource, + }, +#if defined(CFG_HPDC) + [DEVICE_HPDC] = { + .nr_resources = ARRAY_SIZE(hpdc_resource), + .resource = hpdc_resource, + }, +#endif +#if defined(CFG_MACB0) + [DEVICE_MACB0] = { + .regs = (void *)MACB0_BASE, + .nr_resources = ARRAY_SIZE(macb0_resource), + .resource = macb0_resource, + }, +#endif +#if defined(CFG_MACB1) + [DEVICE_MACB1] = { + .regs = (void *)MACB1_BASE, + .nr_resources = ARRAY_SIZE(macb1_resource), + .resource = macb1_resource, + }, +#endif +#if defined(CFG_LCDC) + [DEVICE_LCDC] = { + .nr_resources = ARRAY_SIZE(lcdc_resource), + .resource = lcdc_resource, + }, +#endif +#if defined(CFG_USART0) + [DEVICE_USART0] = { + .regs = (void *)USART0_BASE, + .nr_resources = ARRAY_SIZE(usart0_resource), + .resource = usart0_resource, + }, +#endif +#if defined(CFG_USART1) + [DEVICE_USART1] = { + .regs = (void *)USART1_BASE, + .nr_resources = ARRAY_SIZE(usart1_resource), + .resource = usart1_resource, + }, +#endif +#if defined(CFG_USART2) + [DEVICE_USART2] = { + .regs = (void *)USART2_BASE, + .nr_resources = ARRAY_SIZE(usart2_resource), + .resource = usart2_resource, + }, +#endif +#if defined(CFG_USART3) + [DEVICE_USART3] = { + .regs = (void *)USART3_BASE, + .nr_resources = ARRAY_SIZE(usart3_resource), + .resource = usart3_resource, + }, +#endif +#if defined(CFG_MMCI) + [DEVICE_MMCI] = { + .regs = (void *)MMCI_BASE, + .nr_resources = ARRAY_SIZE(mmci_resource), + .resource = mmci_resource, + }, +#endif +#if defined(CFG_DMAC) + [DEVICE_DMAC] = { + .regs = (void *)DMAC_BASE, + .nr_resources = ARRAY_SIZE(dmac_resource), + .resource = dmac_resource, + }, +#endif +}; diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/ap7000/hebi.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/hebi.c --- u-boot-1.1.4/cpu/at32ap7xxx/ap7000/hebi.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/hebi.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +#include +#include +#include + +void cpu_enable_sdram(void) +{ + const struct device *hmatrix; + + hmatrix = get_device(DEVICE_HMATRIX); + + /* Set the SDRAM_ENABLE bit in the HEBI SFR */ + hmatrix2_writel(hmatrix, SFR4, 1 << 1); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/ap7000/Makefile u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/Makefile --- u-boot-1.1.4/cpu/at32ap7xxx/ap7000/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/Makefile 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,42 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +SRC = hebi.c devices.c +OBJ = $(addsuffix .o,$(basename $(SRC))) + +all: .depend $(LIB) + +$(LIB): $(OBJ) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SRC) + $(CC) -M $(CFLAGS) $(SRC) > $@ + +sinclude .depend + +######################################################################### diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/config.mk u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/config.mk --- u-boot-1.1.4/cpu/at32ap7xxx/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/config.mk 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,22 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/cpu.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/cpu.c --- u-boot-1.1.4/cpu/at32ap7xxx/cpu.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/cpu.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "hsmc3.h" + +int cpu_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + const struct device *hebi; + extern void _evba(void); + char *p; + + gd->cpu_hz = CFG_OSC0_HZ; + + /* fff03400: 00010001 04030402 00050005 10011103 */ + hebi = get_device(DEVICE_HEBI); + hsmc3_writel(hebi, MODE0, 0x00031103); + hsmc3_writel(hebi, CYCLE0, 0x000c000d); + hsmc3_writel(hebi, PULSE0, 0x0b0a0906); + hsmc3_writel(hebi, SETUP0, 0x00010002); + + pm_init(); + + sysreg_write(SYSREG_EVBA, &_evba); + asm volatile("csrf %0" : : "i"(SYSREG_SR_EM_OFFSET)); + gd->console_uart = get_device(CFG_CONSOLE_UART_DEV); + + /* Lock everything that mess with the flash in the icache */ + for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ); + p += CFG_ICACHE_LINESZ) + asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory"); + + return 0; +} + +void enable_interrupts(void) +{ + asm volatile("csrf %0" : : "n"(SYSREG_SR_GM_OFFSET)); +} + +int disable_interrupts(void) +{ + unsigned long sr; + + sr = sysreg_read(SYSREG_SR); + asm volatile("ssrf %0" : : "n"(SYSREG_SR_GM_OFFSET)); + + return SYSREG_GETBF(SR_GM, sr); +} + +void prepare_to_boot(void) +{ + /* Flush both caches and the write buffer */ + asm volatile("cache %0[4], 010\n\t" + "cache %0[0], 000\n\t" + "sync 0" : : "r"(0) : "memory"); +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + /* This will reset the CPU core, caches, MMU and all internal busses */ + dbgreg_write(DBGREG_DC, DBGREG_BIT(DC_RES)); + + /* Flush the pipeline before we declare it a failure */ + asm volatile("sub pc, pc, 4"); + + return -1; +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/dcache_clean.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/dcache_clean.c --- u-boot-1.1.4/cpu/at32ap7xxx/dcache_clean.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/dcache_clean.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +void dcache_clean_range(volatile void *start, size_t size) +{ + unsigned long v, begin, end, linesz; + + linesz = CFG_DCACHE_LINESZ; + + /* You asked for it, you got it */ + begin = (unsigned long)start & ~(linesz - 1); + end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + + for (v = begin; v < end; v += linesz) + dcache_clean_line((void *)v); + + sync_write_buffer(); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/dcache_invalidate.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/dcache_invalidate.c --- u-boot-1.1.4/cpu/at32ap7xxx/dcache_invalidate.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/dcache_invalidate.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +void dcache_invalidate_range(volatile void *start, size_t size) +{ + unsigned long v, begin, end, linesz; + + linesz = CFG_DCACHE_LINESZ; + + /* You asked for it, you got it */ + begin = (unsigned long)start & ~(linesz - 1); + end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + + for (v = begin; v < end; v += linesz) + dcache_invalidate_line((void *)v); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/device.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/device.c --- u-boot-1.1.4/cpu/at32ap7xxx/device.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/device.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +#include "sm.h" + +struct device_state { + int refcount; +}; + +static struct device_state device_state[NR_DEVICES]; + +static int claim_resource(const struct resource *res) +{ + int ret = 0; + + switch (res->type) { + case RESOURCE_GPIO: + ret = gpio_set_func(res->u.gpio.gpio_dev, + res->u.gpio.start, + res->u.gpio.nr_pins, + res->u.gpio.func); + break; + case RESOURCE_CLOCK: + ret = pm_enable_clock(res->u.clock.id, res->u.clock.index); + break; + } + + return ret; +} + +static void free_resource(const struct resource *res) +{ + switch (res->type) { + case RESOURCE_GPIO: + gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start, + res->u.gpio.nr_pins); + break; + case RESOURCE_CLOCK: + pm_disable_clock(res->u.clock.id, res->u.clock.index); + break; + } +} + +static int init_dev(const struct device *dev) +{ + unsigned int i; + int ret = 0; + + for (i = 0; i < dev->nr_resources; i++) { + ret = claim_resource(&dev->resource[i]); + if (ret) + goto cleanup; + } + + return 0; + +cleanup: + while (i--) + free_resource(&dev->resource[i]); + + return ret; +} + +const struct device *get_device(enum device_id devid) +{ + struct device_state *devstate; + const struct device *dev; + unsigned long flags; + int initialized = 0; + int ret = 0; + + devstate = &device_state[devid]; + dev = &chip_device[devid]; + + local_irq_save(flags); + if (devstate->refcount++) + initialized = 1; + local_irq_restore(flags); + + if (!initialized) + ret = init_dev(dev); + + return ret ? NULL : dev; +} + +void put_device(const struct device *dev) +{ + struct device_state *devstate; + unsigned long devid, flags; + + devid = (unsigned long)(dev - chip_device) / sizeof(struct device); + devstate = &device_state[devid]; + + local_irq_save(flags); + devstate--; + if (!devstate) { + unsigned int i; + for (i = 0; i < dev->nr_resources; i++) + free_resource(&dev->resource[i]); + } + local_irq_restore(flags); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/entry.S u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/entry.S --- u-boot-1.1.4/cpu/at32ap7xxx/entry.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/entry.S 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + + .section .text.exception,"ax" + .global _evba + .type _evba,@function + .align 10 +_evba: + .irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 + .align 2 + rjmp unknown_exception + .endr + + .type unknown_exception, @function +unknown_exception: + pushm r0-r12 + sub r8, sp, REG_R12 - REG_R0 - 4 + mov r9, lr + mfsr r10, SYSREG_RAR_EX + mfsr r11, SYSREG_RSR_EX + pushm r8-r11 + mfsr r12, SYSREG_ECR + mov r11, sp + rcall do_unknown_exception +1: rjmp 1b diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/exception.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/exception.c --- u-boot-1.1.4/cpu/at32ap7xxx/exception.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/exception.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +static const char * const cpu_modes[8] = { + "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1", + "Interrupt level 2", "Interrupt level 3", "Exception", "NMI" +}; + +static void dump_mem(const char *str, unsigned long bottom, unsigned long top) +{ + unsigned long p; + int i; + + printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); + + for (p = bottom & ~31; p < top; ) { + printf("%04lx: ", p & 0xffff); + + for (i = 0; i < 8; i++, p += 4) { + unsigned int val; + + if (p < bottom || p >= top) + printf(" "); + else { + val = *(unsigned long *)p; + printf("%08x ", val); + } + } + printf("\n"); + } +} + +void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) +{ + unsigned int mode; + + printf("\n *** Unhandled exception %u at PC=0x%08lx\n", ecr, regs->pc); + + switch (ecr) { + case ECR_BUS_ERROR_WRITE: + case ECR_BUS_ERROR_READ: + printf("Bus error at address 0x%08lx\n", + sysreg_read(SYSREG_BEAR)); + break; + case ECR_TLB_MULTIPLE: + case ECR_INSN_ADDR: + case ECR_TLB_PROTECTION_X: + case ECR_DATA_ADDR_R: + case ECR_DATA_ADDR_W: + case ECR_TLB_PROTECTION_R: + case ECR_TLB_PROTECTION_W: + case ECR_DIRTY_PAGE: + case ECR_TLB_MISS_X: + case ECR_TLB_MISS_R: + case ECR_TLB_MISS_W: + printf("MMU exception at address 0x%08lx\n", + sysreg_read(SYSREG_TLBEAR)); + break; + } + + printf(" pc: %08lx lr: %08lx sp: %08lx r12: %08lx\n", + regs->pc, regs->lr, regs->sp, regs->r12); + printf(" r11: %08lx r10: %08lx r9: %08lx r8: %08lx\n", + regs->r11, regs->r10, regs->r9, regs->r8); + printf(" r7: %08lx r6: %08lx r5: %08lx r4: %08lx\n", + regs->r7, regs->r6, regs->r5, regs->r4); + printf(" r3: %08lx r2: %08lx r1: %08lx r0: %08lx\n", + regs->r3, regs->r2, regs->r1, regs->r0); + printf("Flags: %c%c%c%c%c\n", + regs->sr & SR_Q ? 'Q' : 'q', + regs->sr & SR_V ? 'V' : 'v', + regs->sr & SR_N ? 'N' : 'n', + regs->sr & SR_Z ? 'Z' : 'z', + regs->sr & SR_C ? 'C' : 'c'); + printf("Mode bits: %c%c%c%c%c%c%c%c%c\n", + regs->sr & SR_H ? 'H' : 'h', + regs->sr & SR_R ? 'R' : 'r', + regs->sr & SR_J ? 'J' : 'j', + regs->sr & SR_EM ? 'E' : 'e', + regs->sr & SR_I3M ? '3' : '.', + regs->sr & SR_I2M ? '2' : '.', + regs->sr & SR_I1M ? '1' : '.', + regs->sr & SR_I0M ? '0' : '.', + regs->sr & SR_GM ? 'G' : 'g'); + mode = (regs->sr >> SYSREG_SR_M0_OFFSET) & 7; + printf("CPU Mode: %s\n", cpu_modes[mode]); + + /* Avoid exception loops */ + if (regs->sp >= CFG_INIT_SP_ADDR + || regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE)) + printf("\nStack pointer seems bogus, won't do stack dump\n"); + else + dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR); + + panic("Unhandled exception\n"); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/hsdramc1.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsdramc1.h --- u-boot-1.1.4/cpu/at32ap7xxx/hsdramc1.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsdramc1.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_HSDRAMC1_H__ +#define __ASM_AVR32_HSDRAMC1_H__ + +/* HSDRAMC1 register offsets */ +#define HSDRAMC1_MR 0x0000 +#define HSDRAMC1_TR 0x0004 +#define HSDRAMC1_CR 0x0008 +#define HSDRAMC1_HSR 0x000c +#define HSDRAMC1_LPR 0x0010 +#define HSDRAMC1_IER 0x0014 +#define HSDRAMC1_IDR 0x0018 +#define HSDRAMC1_IMR 0x001c +#define HSDRAMC1_ISR 0x0020 +#define HSDRAMC1_MDR 0x0024 +#define HSDRAMC1_VERSION 0x00fc + +/* Bitfields in MR */ +#define HSDRAMC1_MODE_OFFSET 0 +#define HSDRAMC1_MODE_SIZE 3 + +/* Bitfields in TR */ +#define HSDRAMC1_COUNT_OFFSET 0 +#define HSDRAMC1_COUNT_SIZE 12 + +/* Bitfields in CR */ +#define HSDRAMC1_NC_OFFSET 0 +#define HSDRAMC1_NC_SIZE 2 +#define HSDRAMC1_NR_OFFSET 2 +#define HSDRAMC1_NR_SIZE 2 +#define HSDRAMC1_NB_OFFSET 4 +#define HSDRAMC1_NB_SIZE 1 +#define HSDRAMC1_CAS_OFFSET 5 +#define HSDRAMC1_CAS_SIZE 2 +#define HSDRAMC1_DBW_OFFSET 7 +#define HSDRAMC1_DBW_SIZE 1 +#define HSDRAMC1_TWR_OFFSET 8 +#define HSDRAMC1_TWR_SIZE 4 +#define HSDRAMC1_TRC_OFFSET 12 +#define HSDRAMC1_TRC_SIZE 4 +#define HSDRAMC1_TRP_OFFSET 16 +#define HSDRAMC1_TRP_SIZE 4 +#define HSDRAMC1_TRCD_OFFSET 20 +#define HSDRAMC1_TRCD_SIZE 4 +#define HSDRAMC1_TRAS_OFFSET 24 +#define HSDRAMC1_TRAS_SIZE 4 +#define HSDRAMC1_TXSR_OFFSET 28 +#define HSDRAMC1_TXSR_SIZE 4 + +/* Bitfields in HSR */ +#define HSDRAMC1_DA_OFFSET 0 +#define HSDRAMC1_DA_SIZE 1 + +/* Bitfields in LPR */ +#define HSDRAMC1_LPCB_OFFSET 0 +#define HSDRAMC1_LPCB_SIZE 2 +#define HSDRAMC1_PASR_OFFSET 4 +#define HSDRAMC1_PASR_SIZE 3 +#define HSDRAMC1_TCSR_OFFSET 8 +#define HSDRAMC1_TCSR_SIZE 2 +#define HSDRAMC1_DS_OFFSET 10 +#define HSDRAMC1_DS_SIZE 2 +#define HSDRAMC1_TIMEOUT_OFFSET 12 +#define HSDRAMC1_TIMEOUT_SIZE 2 + +/* Bitfields in IER */ + +/* Bitfields in IDR */ +#define HSDRAMC1_RES_OFFSET 0 +#define HSDRAMC1_RES_SIZE 1 + +/* Bitfields in IMR */ + +/* Bitfields in ISR */ + +/* Bitfields in MDR */ +#define HSDRAMC1_MD_OFFSET 0 +#define HSDRAMC1_MD_SIZE 2 + +/* Bitfields in VERSION */ +#define HSDRAMC1_VERSION_OFFSET 0 +#define HSDRAMC1_VERSION_SIZE 12 +#define HSDRAMC1_MFN_OFFSET 16 +#define HSDRAMC1_MFN_SIZE 3 + +/* Constants for MODE */ +#define HSDRAMC1_MODE_NORMAL 0 +#define HSDRAMC1_MODE_NOP 1 +#define HSDRAMC1_MODE_BANKS_PRECHARGE 2 +#define HSDRAMC1_MODE_LOAD_MODE 3 +#define HSDRAMC1_MODE_AUTO_REFRESH 4 +#define HSDRAMC1_MODE_EXT_LOAD_MODE 5 +#define HSDRAMC1_MODE_POWER_DOWN 6 + +/* Constants for NC */ +#define HSDRAMC1_NC_8_COLUMN_BITS 0 +#define HSDRAMC1_NC_9_COLUMN_BITS 1 +#define HSDRAMC1_NC_10_COLUMN_BITS 2 +#define HSDRAMC1_NC_11_COLUMN_BITS 3 + +/* Constants for NR */ +#define HSDRAMC1_NR_11_ROW_BITS 0 +#define HSDRAMC1_NR_12_ROW_BITS 1 +#define HSDRAMC1_NR_13_ROW_BITS 2 + +/* Constants for NB */ +#define HSDRAMC1_NB_TWO_BANKS 0 +#define HSDRAMC1_NB_FOUR_BANKS 1 + +/* Constants for CAS */ +#define HSDRAMC1_CAS_ONE_CYCLE 1 +#define HSDRAMC1_CAS_TWO_CYCLES 2 + +/* Constants for DBW */ +#define HSDRAMC1_DBW_32_BITS 0 +#define HSDRAMC1_DBW_16_BITS 1 + +/* Constants for TIMEOUT */ +#define HSDRAMC1_TIMEOUT_AFTER_END 0 +#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END 1 +#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END 2 + +/* Constants for MD */ +#define HSDRAMC1_MD_SDRAM 0 +#define HSDRAMC1_MD_LOW_POWER_SDRAM 1 + +/* Bit manipulation macros */ +#define HSDRAMC1_BIT(name) (1 << HSDRAMC1_##name##_OFFSET) +#define HSDRAMC1_BF(name,value) (((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) << HSDRAMC1_##name##_OFFSET) +#define HSDRAMC1_BFEXT(name,value) (((value) >> HSDRAMC1_##name##_OFFSET) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) +#define HSDRAMC1_BFINS(name,value,old) (((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1) << HSDRAMC1_##name##_OFFSET)) | HSDRAMC1_BF(name,value)) + +/* Register access macros */ +#define hsdramc1_readl(port,reg) readl((port)->regs + HSDRAMC1_##reg) +#define hsdramc1_writel(port,reg,value) writel((value), (port)->regs + HSDRAMC1_##reg) + +#endif /* __ASM_AVR32_HSDRAMC1_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsdramc.c --- u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsdramc.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CFG_HSDRAMC +#include +#include + +#include + +#include "hsdramc1.h" + +struct hsdramc { + const struct device *hebi; + void *regs; +}; + +static struct hsdramc hsdramc; + +unsigned long sdram_init(const struct sdram_info *info) +{ + unsigned long *sdram = (unsigned long *)uncached(info->phys_addr); + unsigned long sdram_size; + unsigned long tmp; + unsigned long bus_hz; + unsigned int i; + + hsdramc.hebi = get_device(DEVICE_HEBI); + if (!hsdramc.hebi) + return 0; + + /* FIXME: Both of these lines are complete hacks */ + hsdramc.regs = hsdramc.hebi->regs + 0x400; + bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id); + + cpu_enable_sdram(); + + sdram_size = 1 << (info->row_bits + info->col_bits + + info->bank_bits + 2); + + tmp = (HSDRAMC1_BF(NC, info->col_bits - 8) + | HSDRAMC1_BF(NR, info->row_bits - 11) + | HSDRAMC1_BF(NB, info->bank_bits - 1) + | HSDRAMC1_BF(CAS, info->cas) + | HSDRAMC1_BF(TWR, info->twr) + | HSDRAMC1_BF(TRC, info->trc) + | HSDRAMC1_BF(TRP, info->trp) + | HSDRAMC1_BF(TRCD, info->trcd) + | HSDRAMC1_BF(TRAS, info->tras) + | HSDRAMC1_BF(TXSR, info->txsr)); + hsdramc1_writel(&hsdramc, CR, tmp); + + /* + * Initialization sequence for SDRAM, from the data sheet: + * + * 1. A minimum pause of 200 us is provided to precede any + * signal toggle. + */ + udelay(200); + + /* + * 2. A Precharge All command is issued to the SDRAM + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram); + + /* + * 3. Eight auto-refresh (CBR) cycles are provided + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH); + hsdramc1_readl(&hsdramc, MR); + for (i = 0; i < 8; i++) + writel(0, sdram); + + /* + * 4. A mode register set (MRS) cycle is issued to program + * SDRAM parameters, in particular CAS latency and burst + * length. + * + * CAS from info struct, burst length 1, serial burst type + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram + (info->cas << 4)); + + /* + * 5. A Normal Mode command is provided, 3 clocks after tMRD + * is met. + * + * From the timing diagram, it looks like tMRD is 3 + * cycles...try a dummy read from APB. + */ + hsdramc1_readl(&hsdramc, MR); + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram); + + /* + * 6. Write refresh rate into SDRAMC refresh timer count + * register (refresh rate = timing between refresh cycles). + * + * 15.6 us is a typical value for a burst of length one + */ + hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000); + + printf("SDRAM: %u MB at address 0x%08lx\n", + sdram_size >> 20, info->phys_addr); + + printf("Testing SDRAM..."); + for (i = 0; i < sdram_size / 4; i++) + sdram[i] = i; + + for (i = 0; i < sdram_size / 4; i++) { + tmp = sdram[i]; + if (tmp != i) { + printf("FAILED at address 0x%08lx\n", + info->phys_addr + i * 4); + printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i); + return 0; + } + } + + puts("OK\n"); + + return sdram_size; +} + +#endif /* CFG_HSDRAMC */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/hsmc3.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsmc3.h --- u-boot-1.1.4/cpu/at32ap7xxx/hsmc3.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsmc3.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,156 @@ +/* + * Register definitions for HSMC3 + * + * Static Memory Controller + */ +#ifndef __ASM_AVR32_HSMC3_H__ +#define __ASM_AVR32_HSMC3_H__ + +/* HSMC3 register offsets */ +#define HSMC3_SETUP0 0x0000 +#define HSMC3_PULSE0 0x0004 +#define HSMC3_CYCLE0 0x0008 +#define HSMC3_MODE0 0x000c +#define HSMC3_SETUP1 0x0010 +#define HSMC3_PULSE1 0x0014 +#define HSMC3_CYCLE1 0x0018 +#define HSMC3_MODE1 0x001c +#define HSMC3_SETUP2 0x0020 +#define HSMC3_PULSE2 0x0024 +#define HSMC3_CYCLE2 0x0028 +#define HSMC3_MODE2 0x002c +#define HSMC3_SETUP3 0x0030 +#define HSMC3_PULSE3 0x0034 +#define HSMC3_CYCLE3 0x0038 +#define HSMC3_MODE3 0x003c +#define HSMC3_SETUP4 0x0040 +#define HSMC3_PULSE4 0x0044 +#define HSMC3_CYCLE4 0x0048 +#define HSMC3_MODE4 0x004c +#define HSMC3_SETUP5 0x0050 +#define HSMC3_PULSE5 0x0054 +#define HSMC3_CYCLE5 0x0058 +#define HSMC3_MODE5 0x005c + +/* Bitfields in SETUP0 */ +#define HSMC3_NWE_SETUP_OFFSET 0 +#define HSMC3_NWE_SETUP_SIZE 6 +#define HSMC3_NCS_WR_SETUP_OFFSET 8 +#define HSMC3_NCS_WR_SETUP_SIZE 6 +#define HSMC3_NRD_SETUP_OFFSET 16 +#define HSMC3_NRD_SETUP_SIZE 6 +#define HSMC3_NCS_RD_SETUP_OFFSET 24 +#define HSMC3_NCS_RD_SETUP_SIZE 6 + +/* Bitfields in PULSE0 */ +#define HSMC3_NWE_PULSE_OFFSET 0 +#define HSMC3_NWE_PULSE_SIZE 7 +#define HSMC3_NCS_WR_PULSE_OFFSET 8 +#define HSMC3_NCS_WR_PULSE_SIZE 7 +#define HSMC3_NRD_PULSE_OFFSET 16 +#define HSMC3_NRD_PULSE_SIZE 7 +#define HSMC3_NCS_RD_PULSE_OFFSET 24 +#define HSMC3_NCS_RD_PULSE_SIZE 7 + +/* Bitfields in CYCLE0 */ +#define HSMC3_NWE_CYCLE_OFFSET 0 +#define HSMC3_NWE_CYCLE_SIZE 9 +#define HSMC3_NRD_CYCLE_OFFSET 16 +#define HSMC3_NRD_CYCLE_SIZE 9 + +/* Bitfields in MODE0 */ +#define HSMC3_READ_MODE_OFFSET 0 +#define HSMC3_READ_MODE_SIZE 1 +#define HSMC3_WRITE_MODE_OFFSET 1 +#define HSMC3_WRITE_MODE_SIZE 1 +#define HSMC3_EXNW_MODE_OFFSET 4 +#define HSMC3_EXNW_MODE_SIZE 2 +#define HSMC3_BAT_OFFSET 8 +#define HSMC3_BAT_SIZE 1 +#define HSMC3_DBW_OFFSET 12 +#define HSMC3_DBW_SIZE 2 +#define HSMC3_TDF_CYCLES_OFFSET 16 +#define HSMC3_TDF_CYCLES_SIZE 4 +#define HSMC3_TDF_MODE_OFFSET 20 +#define HSMC3_TDF_MODE_SIZE 1 +#define HSMC3_PMEN_OFFSET 24 +#define HSMC3_PMEN_SIZE 1 +#define HSMC3_PS_OFFSET 28 +#define HSMC3_PS_SIZE 2 + +/* Bitfields in SETUP1 */ + +/* Bitfields in PULSE1 */ + +/* Bitfields in CYCLE1 */ + +/* Bitfields in MODE1 */ +#define HSMC3_PD_OFFSET 28 +#define HSMC3_PD_SIZE 2 + +/* Bitfields in SETUP2 */ + +/* Bitfields in PULSE2 */ + +/* Bitfields in CYCLE2 */ + +/* Bitfields in MODE2 */ + +/* Bitfields in SETUP3 */ + +/* Bitfields in PULSE3 */ + +/* Bitfields in CYCLE3 */ + +/* Bitfields in MODE3 */ + +/* Bitfields in SETUP4 */ + +/* Bitfields in PULSE4 */ + +/* Bitfields in CYCLE4 */ + +/* Bitfields in MODE4 */ + +/* Bitfields in SETUP5 */ + +/* Bitfields in PULSE5 */ + +/* Bitfields in CYCLE5 */ + +/* Bitfields in MODE5 */ + +/* Constants for READ_MODE */ +#define HSMC3_READ_MODE_NCS_CONTROLLED 0 +#define HSMC3_READ_MODE_NRD_CONTROLLED 1 + +/* Constants for WRITE_MODE */ +#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0 +#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1 + +/* Constants for EXNW_MODE */ +#define HSMC3_EXNW_MODE_DISABLED 0 +#define HSMC3_EXNW_MODE_RESERVED 1 +#define HSMC3_EXNW_MODE_FROZEN 2 +#define HSMC3_EXNW_MODE_READY 3 + +/* Constants for BAT */ +#define HSMC3_BAT_BYTE_SELECT 0 +#define HSMC3_BAT_BYTE_WRITE 1 + +/* Constants for DBW */ +#define HSMC3_DBW_8_BITS 0 +#define HSMC3_DBW_16_BITS 1 +#define HSMC3_DBW_32_BITS 2 + +/* Bit manipulation macros */ +#define HSMC3_BIT(name) (1 << HSMC3_##name##_OFFSET) +#define HSMC3_BF(name,value) (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) << HSMC3_##name##_OFFSET) +#define HSMC3_BFEXT(name,value) (((value) >> HSMC3_##name##_OFFSET) & ((1 << HSMC3_##name##_SIZE) - 1)) +#define HSMC3_BFINS(name,value,old) (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) << HSMC3_##name##_OFFSET)) | HSMC3_BF(name,value)) + +/* Register access macros */ +#define hsmc3_readl(port,reg) readl((port)->regs + HSMC3_##reg) +#define hsmc3_writel(port,reg,value) writel((value), (port)->regs + HSMC3_##reg) + +#endif /* __ASM_AVR32_HSMC3_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/Makefile u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/Makefile --- u-boot-1.1.4/cpu/at32ap7xxx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/Makefile 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,46 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.S +START_OBJ = start.o +SRC = cpu.c hsdramc.c mmc.c entry.S exception.c +SRC += dcache_clean.c dcache_invalidate.c +SRC += device.c pm.c pio.c +OBJ = $(addsuffix .o,$(basename $(SRC))) + +all: .depend $(START_OBJ) $(LIB) + +$(LIB): $(OBJ) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(START) $(SRC) + $(CC) -M $(CFLAGS) $(START) $(SRC) > $@ + +sinclude .depend + +######################################################################### diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/mmc.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/mmc.c --- u-boot-1.1.4/cpu/at32ap7xxx/mmc.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/mmc.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,499 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define xDEBUG +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "mmci.h" + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args) +#else +#define pr_debug(...) do { } while(0) +#endif + +#ifdef CONFIG_MMC + +#ifndef CFG_MMC_CLK_OD +#define CFG_MMC_CLK_OD 150000 +#endif + +#ifndef CFG_MMC_CLK_PP +#define CFG_MMC_CLK_PP 5000000 +#endif + +#ifndef CFG_MMC_BLKLEN +#define CFG_MMC_BLKLEN 512 +#endif + +#ifndef CFG_OP_COND +#define CFG_OP_COND 0x00100000 +#endif + +#define MMC_DEFAULT_RCA 1 + +static unsigned long status; +static unsigned long mmc_bread(int dev, unsigned long start, + lbaint_t blkcnt, unsigned long *buffer); + +struct mmci { + void *regs; + unsigned int rca; + block_dev_desc_t blkdev; + const struct device *dev; +}; + +struct mmci mmci = { + .regs = (void *)MMCI_BASE, + .blkdev = { + .if_type = IF_TYPE_MMC, + .block_read = mmc_bread, + }, +}; + +block_dev_desc_t *mmc_get_dev(int dev) +{ + return &mmci.blkdev; +} + +static void mci_set_mode(unsigned long hz, unsigned long blklen) +{ + unsigned long bus_hz; + unsigned long clkdiv; + + bus_hz = pm_get_clock_freq(mmci.dev->resource[0].u.clock.id); + clkdiv = (bus_hz / hz) / 2 - 1; + + pr_debug("mmc: setting clock %lu Hz, block size %lu\n", + hz, blklen); + + if (clkdiv & ~255UL) { + clkdiv = 255; + printf("mmc: clock %lu too low; setting CLKDIV to 255\n", + hz); + } + + blklen &= 0xfffc; + mmci_writel(&mmci, MCI_MR, (MMCI_MKBF(MCI_MR_CLKDIV, clkdiv) + | MMCI_MKBF(MCI_MR_BLKLEN, blklen))); +} + +#define RESP_NO_CRC 1 +#define R1 MMCI_MKBF(MCI_CMDR_RSPTYP, 1) +#define R2 MMCI_MKBF(MCI_CMDR_RSPTYP, 2) +#define R3 (R1 | RESP_NO_CRC) +#define R6 R1 +#define NID MMCI_MKBF(MCI_CMDR_MAXLAT, 0) +#define NCR MMCI_MKBF(MCI_CMDR_MAXLAT, 1) +#define TRCMD_START MMCI_MKBF(MCI_CMDR_TRCMD, 1) +#define TRDIR_READ MMCI_MKBF(MCI_CMDR_TRDIR, 1) +#define TRTYP_BLOCK MMCI_MKBF(MCI_CMDR_TRTYP, 0) +#define INIT_CMD MMCI_MKBF(MCI_CMDR_SPCMD, 1) +#define OPEN_DRAIN MMCI_MKBF(MCI_CMDR_OPDCMD, 1) + +#define ERROR_FLAGS (MMCI_BIT(MCI_SR_DTOE) \ + | MMCI_BIT(MCI_SR_RDIRE) \ + | MMCI_BIT(MCI_SR_RENDE) \ + | MMCI_BIT(MCI_SR_RINDE) \ + | MMCI_BIT(MCI_SR_RTOE)) + +static int +mmc_cmd(unsigned long cmd, unsigned long arg, + void *resp, unsigned long flags) +{ + unsigned long *response = resp; + int i, response_words = 0; + unsigned long error_flags; + + pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", + cmd, arg, flags); + + error_flags = ERROR_FLAGS; + if (!(flags & RESP_NO_CRC)) + error_flags |= MMCI_BIT(MCI_SR_RCRCE); + + flags &= ~MMCI_MKBF(MCI_CMDR_CMDNB, ~0UL); + + if (MMCI_GETBF(MCI_CMDR_RSPTYP, flags) == 1) + response_words = 1; + else if (MMCI_GETBF(MCI_CMDR_RSPTYP, flags) == 2) + response_words = 4; + + mmci_writel(&mmci, MCI_ARGR, arg); + mmci_writel(&mmci, MCI_CMDR, cmd | flags); + do { + udelay(40); + status = mmci_readl(&mmci, MCI_SR); + } while (!(status & MMCI_BIT(MCI_SR_CMDRDY))); + + pr_debug("mmc: status 0x%08lx\n", status); + + if (status & ERROR_FLAGS) { + printf("mmc: command %lu failed (status: 0x%08lx)\n", + cmd, status); + return -EIO; + } + + if (response_words) + pr_debug("mmc: response:"); + + for (i = 0; i < response_words; i++) { + response[i] = mmci_readl(&mmci, MCI_RSPR); + pr_debug(" %08lx", response[i]); + } + pr_debug("\n"); + + return 0; +} + +static int mmc_acmd(unsigned long cmd, unsigned long arg, + void *resp, unsigned long flags) +{ + unsigned long aresp[4]; + int ret; + + /* + * Seems like the APP_CMD part of an ACMD has 64 cycles max + * latency even though the ACMD part doesn't. This isn't + * entirely clear in the SD Card spec, but some cards refuse + * to work if we attempt to use 5 cycles max latency here... + */ + ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp, + R1 | NCR | (flags & OPEN_DRAIN)); + if (ret) + return ret; + if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD) + return -ENODEV; + + ret = mmc_cmd(cmd, arg, resp, flags); + return ret; +} + +static unsigned long +mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, + unsigned long *buffer) +{ + int ret, i = 0; + unsigned long resp[4]; + unsigned long card_status, data; + unsigned long wordcount; + struct mmci *mmc = &mmci; + + if (blkcnt == 0) + return 0; + + pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n", + dev, start, blkcnt); + + /* Put the device into Transfer state */ + ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc->rca << 16, resp, R1 | NCR); + if (ret) goto fail; + + /* Set block length */ + ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc->blkdev.blksz, resp, R1 | NCR); + if (ret) goto fail; + + pr_debug("MCI_DTOR = %08lx\n", mmci_readl(&mmci, MCI_DTOR)); + + for (i = 0; i < blkcnt; i++, start++) { + ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, + start * mmc->blkdev.blksz, resp, + (R1 | NCR | TRCMD_START | TRDIR_READ + | TRTYP_BLOCK)); + if (ret) goto fail; + + ret = -EIO; + wordcount = 0; + do { + do { + status = mmci_readl(&mmci, MCI_SR); + if (status & (ERROR_FLAGS + | MMCI_BIT(MCI_SR_OVRE))) + goto fail; + } while (!(status & MMCI_BIT(MCI_SR_RXRDY))); + + if (status & MMCI_BIT(MCI_SR_RXRDY)) { + data = mmci_readl(&mmci, MCI_RDR); + // pr_debug("%x\n", data); + *buffer++ = data; + wordcount++; + } + } while(wordcount < (512 / 4)); + + pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount); + + do { + status = mmci_readl(&mmci, MCI_SR); + } while (!(status & MMCI_BIT(MCI_SR_BLKE))); + + putc('.'); + } + +out: + /* Put the device back into Standby state */ + mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + return i; + +fail: + printf("mmc: bread failed, SR = %08lx", status); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc->rca << 16, &card_status, R1 | NCR); + printf(", card status = %08lx\n", card_status); + goto out; +} + +static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) +{ + cid->mid = resp[0] >> 24; + cid->oid = (resp[0] >> 8) & 0xffff; + cid->pnm[0] = resp[0]; + cid->pnm[1] = resp[1] >> 24; + cid->pnm[2] = resp[1] >> 16; + cid->pnm[3] = resp[1] >> 8; + cid->pnm[4] = resp[1]; + cid->pnm[5] = resp[2] >> 24; + cid->pnm[6] = 0; + cid->prv = resp[2] >> 16; + cid->psn = (resp[2] << 16) | (resp[3] >> 16); + cid->mdt = resp[3] >> 8; +} + +static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) +{ + cid->mid = resp[0] >> 24; + cid->oid = (resp[0] >> 8) & 0xffff; + cid->pnm[0] = resp[0]; + cid->pnm[1] = resp[1] >> 24; + cid->pnm[2] = resp[1] >> 16; + cid->pnm[3] = resp[1] >> 8; + cid->pnm[4] = resp[1]; + cid->pnm[5] = 0; + cid->pnm[6] = 0; + cid->prv = resp[2] >> 24; + cid->psn = (resp[2] << 8) | (resp[3] >> 24); + cid->mdt = (resp[3] >> 8) & 0x0fff; +} + +static void mmc_dump_cid(const struct mmc_cid *cid) +{ + printf("Manufacturer ID: %02lX\n", cid->mid); + printf("OEM/Application ID: %04lX\n", cid->oid); + printf("Product name: %s\n", cid->pnm); + printf("Product Revision: %lu.%lu\n", + cid->prv >> 4, cid->prv & 0x0f); + printf("Product Serial Number: %lu\n", cid->psn); + printf("Manufacturing Date: %02lu/%02lu\n", + cid->mdt >> 4, cid->mdt & 0x0f); +} + +static void mmc_dump_csd(const struct mmc_csd *csd) +{ + unsigned long *csd_raw = (unsigned long *)csd; + printf("CSD data: %08lx %08lx %08lx %08lx\n", + csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); + printf("CSD structure version: 1.%u\n", csd->csd_structure); + printf("MMC System Spec version: %u\n", csd->spec_vers); + printf("Card command classes: %03x\n", csd->ccc); + printf("Read block length: %u\n", 1 << csd->read_bl_len); + if (csd->read_bl_partial) + puts("Supports partial reads\n"); + else + puts("Does not support partial reads\n"); + printf("Write block length: %u\n", 1 << csd->write_bl_len); + if (csd->write_bl_partial) + puts("Supports partial writes\n"); + else + puts("Does not support partial writes\n"); + if (csd->wp_grp_enable) + printf("Supports group WP: %u\n", csd->wp_grp_size + 1); + else + puts("Does not support group WP\n"); + printf("Card capacity: %u bytes\n", + (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) * + (1 << csd->read_bl_len)); + printf("File format: %u/%u\n", + csd->file_format_grp, csd->file_format); + puts("Write protection: "); + if (csd->perm_write_protect) + puts(" permanent"); + if (csd->tmp_write_protect) + puts(" temporary"); + putc('\n'); +} + +static int mmc_idle_cards(void) +{ + int ret; + + /* Reset and initialize all cards */ + ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); + if (ret) + return ret; + + /* Keep the bus idle for 74 clock cycles */ + return mmc_cmd(0, 0, NULL, INIT_CMD); +} + +static int sd_init_card(struct mmci *mmc, struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + for (i = 0; i < 100; i++) { + ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_OP_COND, + resp, R3 | NID); + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID); + if (ret) + return ret; + sd_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Get RCA of the card that responded */ + ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); + if (ret) + return ret; + + mmc->rca = resp[0] >> 16; + if (verbose) + printf("SD Card detected (RCA %u)\n", mmc->rca); + return 0; +} + +static int mmc_init_card(struct mmci *mmc, struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + for (i = 0; i < 100; i++) { + ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_OP_COND, resp, + R3 | NID | OPEN_DRAIN); + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + /* Get CID of all cards. FIXME: Support more than one card */ + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN); + if (ret) + return ret; + mmc_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Set Relative Address of the card that responded */ + ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc->rca << 16, resp, + R1 | NCR | OPEN_DRAIN); + return ret; +} + +int mmc_init(int verbose) +{ + struct mmc_cid cid; + struct mmc_csd csd; + int ret; + + if (!mmci.dev) { + mmci.dev = get_device(DEVICE_MMCI); + mmci.regs = mmci.dev->regs; + } + + /* Initialize controller */ + mmci_writel(&mmci, MCI_CR, MMCI_BIT(MCI_CR_SWRST)); + mmci_writel(&mmci, MCI_CR, MMCI_BIT(MCI_CR_MCIEN)); + mmci_writel(&mmci, MCI_DTOR, 0x5f); + mmci_writel(&mmci, MCI_IDR, ~0UL); + mci_set_mode(CFG_MMC_CLK_OD, CFG_MMC_BLKLEN); + + ret = sd_init_card(&mmci, &cid, verbose); + if (ret) { + mmci.rca = MMC_DEFAULT_RCA; + ret = mmc_init_card(&mmci, &cid, verbose); + } + if (ret) + return ret; + + /* Get CSD from the card */ + ret = mmc_cmd(MMC_CMD_SEND_CSD, mmci.rca << 16, &csd, R2 | NCR); + if (ret) + return ret; + if (verbose) + mmc_dump_csd(&csd); + + /* Initialize the blockdev structure */ + sprintf(mmci.blkdev.vendor, + "Man %02x%04x Snr %08x", + cid.mid, cid.oid, cid.psn); + strncpy(mmci.blkdev.product, cid.pnm, sizeof(mmci.blkdev.product)); + sprintf(mmci.blkdev.revision, + "%x %x", cid.prv >> 4, cid.prv & 0x0f); + mmci.blkdev.dev = 0; + mmci.blkdev.blksz = 1 << csd.read_bl_len; + mmci.blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); + + mci_set_mode(CFG_MMC_CLK_PP, mmci.blkdev.blksz); + +#if 0 + if (fat_register_device(&mmci.blkdev, 1)) + printf("Could not register MMC fat device\n"); +#else + init_part(&mmci.blkdev); +#endif + + return 0; +} + +int mmc_read(ulong src, uchar *dst, int size) +{ + return -ENOSYS; +} + +int mmc_write(uchar *src, ulong dst, int size) +{ + return -ENOSYS; +} + +int mmc2info(ulong addr) +{ + return 0; +} + +#endif /* CONFIG_MMC */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/mmci.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/mmci.h --- u-boot-1.1.4/cpu/at32ap7xxx/mmci.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/mmci.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PERIPH_MMCI_H__ +#define __ASM_AVR32_PERIPH_MMCI_H__ + +#define MMCI_MCI_ARGR 0x00000010 +# define MMCI_MCI_ARGR_ARG_OFFSET 0 +# define MMCI_MCI_ARGR_ARG_SIZE 32 +#define MMCI_MCI_CMDR 0x00000014 +# define MMCI_MCI_CMDR_CMDNB_OFFSET 0 +# define MMCI_MCI_CMDR_CMDNB_SIZE 6 +# define MMCI_MCI_CMDR_MAXLAT_OFFSET 12 +# define MMCI_MCI_CMDR_MAXLAT_SIZE 1 +# define MMCI_MCI_CMDR_OPDCMD_OFFSET 11 +# define MMCI_MCI_CMDR_OPDCMD_SIZE 1 +# define MMCI_MCI_CMDR_RSPTYP_OFFSET 6 +# define MMCI_MCI_CMDR_RSPTYP_SIZE 2 +# define MMCI_MCI_CMDR_SPCMD_OFFSET 8 +# define MMCI_MCI_CMDR_SPCMD_SIZE 3 +# define MMCI_MCI_CMDR_TRCMD_OFFSET 16 +# define MMCI_MCI_CMDR_TRCMD_SIZE 2 +# define MMCI_MCI_CMDR_TRDIR_OFFSET 18 +# define MMCI_MCI_CMDR_TRDIR_SIZE 1 +# define MMCI_MCI_CMDR_TRTYP_OFFSET 19 +# define MMCI_MCI_CMDR_TRTYP_SIZE 2 +#define MMCI_MCI_CR 0x00000000 +# define MMCI_MCI_CR_MCIDIS_OFFSET 1 +# define MMCI_MCI_CR_MCIDIS_SIZE 1 +# define MMCI_MCI_CR_MCIEN_OFFSET 0 +# define MMCI_MCI_CR_MCIEN_SIZE 1 +# define MMCI_MCI_CR_PWSDIS_OFFSET 3 +# define MMCI_MCI_CR_PWSDIS_SIZE 1 +# define MMCI_MCI_CR_PWSEN_OFFSET 2 +# define MMCI_MCI_CR_PWSEN_SIZE 1 +# define MMCI_MCI_CR_SWRST_OFFSET 7 +# define MMCI_MCI_CR_SWRST_SIZE 1 +#define MMCI_MCI_DTOR 0x00000008 +# define MMCI_MCI_DTOR_DTOCYC_OFFSET 0 +# define MMCI_MCI_DTOR_DTOCYC_SIZE 4 +# define MMCI_MCI_DTOR_DTOMUL_OFFSET 4 +# define MMCI_MCI_DTOR_DTOMUL_SIZE 3 +#define MMCI_MCI_IDR 0x00000048 +# define MMCI_MCI_IDR_BLKE_OFFSET 3 +# define MMCI_MCI_IDR_BLKE_SIZE 1 +# define MMCI_MCI_IDR_CMDRDY_OFFSET 0 +# define MMCI_MCI_IDR_CMDRDY_SIZE 1 +# define MMCI_MCI_IDR_DCRCE_OFFSET 21 +# define MMCI_MCI_IDR_DCRCE_SIZE 1 +# define MMCI_MCI_IDR_DTIP_OFFSET 4 +# define MMCI_MCI_IDR_DTIP_SIZE 1 +# define MMCI_MCI_IDR_DTOE_OFFSET 22 +# define MMCI_MCI_IDR_DTOE_SIZE 1 +# define MMCI_MCI_IDR_ENDRX_OFFSET 6 +# define MMCI_MCI_IDR_ENDRX_SIZE 1 +# define MMCI_MCI_IDR_ENDTX_OFFSET 7 +# define MMCI_MCI_IDR_ENDTX_SIZE 1 +# define MMCI_MCI_IDR_NOTBUSY_OFFSET 5 +# define MMCI_MCI_IDR_NOTBUSY_SIZE 1 +# define MMCI_MCI_IDR_OVRE_OFFSET 30 +# define MMCI_MCI_IDR_OVRE_SIZE 1 +# define MMCI_MCI_IDR_RCRCE_OFFSET 18 +# define MMCI_MCI_IDR_RCRCE_SIZE 1 +# define MMCI_MCI_IDR_RDIRE_OFFSET 17 +# define MMCI_MCI_IDR_RDIRE_SIZE 1 +# define MMCI_MCI_IDR_RENDE_OFFSET 19 +# define MMCI_MCI_IDR_RENDE_SIZE 1 +# define MMCI_MCI_IDR_RINDE_OFFSET 16 +# define MMCI_MCI_IDR_RINDE_SIZE 1 +# define MMCI_MCI_IDR_RTOE_OFFSET 20 +# define MMCI_MCI_IDR_RTOE_SIZE 1 +# define MMCI_MCI_IDR_RXBUFF_OFFSET 14 +# define MMCI_MCI_IDR_RXBUFF_SIZE 1 +# define MMCI_MCI_IDR_RXRDY_OFFSET 1 +# define MMCI_MCI_IDR_RXRDY_SIZE 1 +# define MMCI_MCI_IDR_TXBUFE_OFFSET 15 +# define MMCI_MCI_IDR_TXBUFE_SIZE 1 +# define MMCI_MCI_IDR_TXRDY_OFFSET 2 +# define MMCI_MCI_IDR_TXRDY_SIZE 1 +# define MMCI_MCI_IDR_UNRE_OFFSET 31 +# define MMCI_MCI_IDR_UNRE_SIZE 1 +#define MMCI_MCI_IER 0x00000044 +# define MMCI_MCI_IER_BLKE_OFFSET 3 +# define MMCI_MCI_IER_BLKE_SIZE 1 +# define MMCI_MCI_IER_CMDRDY_OFFSET 0 +# define MMCI_MCI_IER_CMDRDY_SIZE 1 +# define MMCI_MCI_IER_DCRCE_OFFSET 21 +# define MMCI_MCI_IER_DCRCE_SIZE 1 +# define MMCI_MCI_IER_DTIP_OFFSET 4 +# define MMCI_MCI_IER_DTIP_SIZE 1 +# define MMCI_MCI_IER_DTOE_OFFSET 22 +# define MMCI_MCI_IER_DTOE_SIZE 1 +# define MMCI_MCI_IER_ENDRX_OFFSET 6 +# define MMCI_MCI_IER_ENDRX_SIZE 1 +# define MMCI_MCI_IER_ENDTX_OFFSET 7 +# define MMCI_MCI_IER_ENDTX_SIZE 1 +# define MMCI_MCI_IER_NOTBUSY_OFFSET 5 +# define MMCI_MCI_IER_NOTBUSY_SIZE 1 +# define MMCI_MCI_IER_OVRE_OFFSET 30 +# define MMCI_MCI_IER_OVRE_SIZE 1 +# define MMCI_MCI_IER_RCRCE_OFFSET 18 +# define MMCI_MCI_IER_RCRCE_SIZE 1 +# define MMCI_MCI_IER_RDIRE_OFFSET 17 +# define MMCI_MCI_IER_RDIRE_SIZE 1 +# define MMCI_MCI_IER_RENDE_OFFSET 19 +# define MMCI_MCI_IER_RENDE_SIZE 1 +# define MMCI_MCI_IER_RINDE_OFFSET 16 +# define MMCI_MCI_IER_RINDE_SIZE 1 +# define MMCI_MCI_IER_RTOE_OFFSET 20 +# define MMCI_MCI_IER_RTOE_SIZE 1 +# define MMCI_MCI_IER_RXBUFF_OFFSET 14 +# define MMCI_MCI_IER_RXBUFF_SIZE 1 +# define MMCI_MCI_IER_RXRDY_OFFSET 1 +# define MMCI_MCI_IER_RXRDY_SIZE 1 +# define MMCI_MCI_IER_TXBUFE_OFFSET 15 +# define MMCI_MCI_IER_TXBUFE_SIZE 1 +# define MMCI_MCI_IER_TXRDY_OFFSET 2 +# define MMCI_MCI_IER_TXRDY_SIZE 1 +# define MMCI_MCI_IER_UNRE_OFFSET 31 +# define MMCI_MCI_IER_UNRE_SIZE 1 +#define MMCI_MCI_IMR 0x0000004c +# define MMCI_MCI_IMR_BLKE_OFFSET 3 +# define MMCI_MCI_IMR_BLKE_SIZE 1 +# define MMCI_MCI_IMR_CMDRDY_OFFSET 0 +# define MMCI_MCI_IMR_CMDRDY_SIZE 1 +# define MMCI_MCI_IMR_DCRCE_OFFSET 21 +# define MMCI_MCI_IMR_DCRCE_SIZE 1 +# define MMCI_MCI_IMR_DTIP_OFFSET 4 +# define MMCI_MCI_IMR_DTIP_SIZE 1 +# define MMCI_MCI_IMR_DTOE_OFFSET 22 +# define MMCI_MCI_IMR_DTOE_SIZE 1 +# define MMCI_MCI_IMR_ENDRX_OFFSET 6 +# define MMCI_MCI_IMR_ENDRX_SIZE 1 +# define MMCI_MCI_IMR_ENDTX_OFFSET 7 +# define MMCI_MCI_IMR_ENDTX_SIZE 1 +# define MMCI_MCI_IMR_NOTBUSY_OFFSET 5 +# define MMCI_MCI_IMR_NOTBUSY_SIZE 1 +# define MMCI_MCI_IMR_OVRE_OFFSET 30 +# define MMCI_MCI_IMR_OVRE_SIZE 1 +# define MMCI_MCI_IMR_RCRCE_OFFSET 18 +# define MMCI_MCI_IMR_RCRCE_SIZE 1 +# define MMCI_MCI_IMR_RDIRE_OFFSET 17 +# define MMCI_MCI_IMR_RDIRE_SIZE 1 +# define MMCI_MCI_IMR_RENDE_OFFSET 19 +# define MMCI_MCI_IMR_RENDE_SIZE 1 +# define MMCI_MCI_IMR_RINDE_OFFSET 16 +# define MMCI_MCI_IMR_RINDE_SIZE 1 +# define MMCI_MCI_IMR_RTOE_OFFSET 20 +# define MMCI_MCI_IMR_RTOE_SIZE 1 +# define MMCI_MCI_IMR_RXBUFF_OFFSET 14 +# define MMCI_MCI_IMR_RXBUFF_SIZE 1 +# define MMCI_MCI_IMR_RXRDY_OFFSET 1 +# define MMCI_MCI_IMR_RXRDY_SIZE 1 +# define MMCI_MCI_IMR_TXBUFE_OFFSET 15 +# define MMCI_MCI_IMR_TXBUFE_SIZE 1 +# define MMCI_MCI_IMR_TXRDY_OFFSET 2 +# define MMCI_MCI_IMR_TXRDY_SIZE 1 +# define MMCI_MCI_IMR_UNRE_OFFSET 31 +# define MMCI_MCI_IMR_UNRE_SIZE 1 +#define MMCI_MCI_MR 0x00000004 +# define MMCI_MCI_MR_BLKLEN_OFFSET 16 +# define MMCI_MCI_MR_BLKLEN_SIZE 16 +# define MMCI_MCI_MR_CLKDIV_OFFSET 0 +# define MMCI_MCI_MR_CLKDIV_SIZE 8 +# define MMCI_MCI_MR_PDCMODE_OFFSET 15 +# define MMCI_MCI_MR_PDCMODE_SIZE 1 +# define MMCI_MCI_MR_PDCPADV_OFFSET 14 +# define MMCI_MCI_MR_PDCPADV_SIZE 1 +# define MMCI_MCI_MR_PWSDIV_OFFSET 8 +# define MMCI_MCI_MR_PWSDIV_SIZE 3 +#define MMCI_MCI_RDR 0x00000030 +# define MMCI_MCI_RDR_DATA_OFFSET 0 +# define MMCI_MCI_RDR_DATA_SIZE 32 +#define MMCI_MCI_RSPR 0x00000020 +# define MMCI_MCI_RSPR_RSP_OFFSET 0 +# define MMCI_MCI_RSPR_RSP_SIZE 32 +#define MMCI_MCI_RSPR1 0x00000024 +# define MMCI_MCI_RSPR1_RSP_OFFSET 0 +# define MMCI_MCI_RSPR1_RSP_SIZE 32 +#define MMCI_MCI_RSPR2 0x00000028 +# define MMCI_MCI_RSPR2_RSP_OFFSET 0 +# define MMCI_MCI_RSPR2_RSP_SIZE 32 +#define MMCI_MCI_RSPR3 0x0000002c +# define MMCI_MCI_RSPR3_RSP_OFFSET 0 +# define MMCI_MCI_RSPR3_RSP_SIZE 32 +#define MMCI_MCI_SDCR 0x0000000c +# define MMCI_MCI_SDCR_SCDBUS_OFFSET 7 +# define MMCI_MCI_SDCR_SCDBUS_SIZE 1 +# define MMCI_MCI_SDCR_SCDSEL_OFFSET 0 +# define MMCI_MCI_SDCR_SCDSEL_SIZE 4 +#define MMCI_MCI_SR 0x00000040 +# define MMCI_MCI_SR_BLKE_OFFSET 3 +# define MMCI_MCI_SR_BLKE_SIZE 1 +# define MMCI_MCI_SR_CMDRDY_OFFSET 0 +# define MMCI_MCI_SR_CMDRDY_SIZE 1 +# define MMCI_MCI_SR_DCRCE_OFFSET 21 +# define MMCI_MCI_SR_DCRCE_SIZE 1 +# define MMCI_MCI_SR_DTIP_OFFSET 4 +# define MMCI_MCI_SR_DTIP_SIZE 1 +# define MMCI_MCI_SR_DTOE_OFFSET 22 +# define MMCI_MCI_SR_DTOE_SIZE 1 +# define MMCI_MCI_SR_ENDRX_OFFSET 6 +# define MMCI_MCI_SR_ENDRX_SIZE 1 +# define MMCI_MCI_SR_ENDTX_OFFSET 7 +# define MMCI_MCI_SR_ENDTX_SIZE 1 +# define MMCI_MCI_SR_NOTBUSY_OFFSET 5 +# define MMCI_MCI_SR_NOTBUSY_SIZE 1 +# define MMCI_MCI_SR_OVRE_OFFSET 30 +# define MMCI_MCI_SR_OVRE_SIZE 1 +# define MMCI_MCI_SR_RCRCE_OFFSET 18 +# define MMCI_MCI_SR_RCRCE_SIZE 1 +# define MMCI_MCI_SR_RDIRE_OFFSET 17 +# define MMCI_MCI_SR_RDIRE_SIZE 1 +# define MMCI_MCI_SR_RENDE_OFFSET 19 +# define MMCI_MCI_SR_RENDE_SIZE 1 +# define MMCI_MCI_SR_RINDE_OFFSET 16 +# define MMCI_MCI_SR_RINDE_SIZE 1 +# define MMCI_MCI_SR_RTOE_OFFSET 20 +# define MMCI_MCI_SR_RTOE_SIZE 1 +# define MMCI_MCI_SR_RXBUFF_OFFSET 14 +# define MMCI_MCI_SR_RXBUFF_SIZE 1 +# define MMCI_MCI_SR_RXRDY_OFFSET 1 +# define MMCI_MCI_SR_RXRDY_SIZE 1 +# define MMCI_MCI_SR_TXBUFE_OFFSET 15 +# define MMCI_MCI_SR_TXBUFE_SIZE 1 +# define MMCI_MCI_SR_TXRDY_OFFSET 2 +# define MMCI_MCI_SR_TXRDY_SIZE 1 +# define MMCI_MCI_SR_UNRE_OFFSET 31 +# define MMCI_MCI_SR_UNRE_SIZE 1 +#define MMCI_MCI_TDR 0x00000034 +# define MMCI_MCI_TDR_DATA_OFFSET 0 +# define MMCI_MCI_TDR_DATA_SIZE 32 +#define MMCI_MCI_VERSION 0x000000fc +# define MMCI_MCI_VERSION_MFN_OFFSET 16 +# define MMCI_MCI_VERSION_MFN_SIZE 3 +# define MMCI_MCI_VERSION_VERSION_OFFSET 0 +# define MMCI_MCI_VERSION_VERSION_SIZE 12 + +#define MMCI_BIT(name) (1 << MMCI_##name##_OFFSET) +#define MMCI_MKBF(name,value) (((value) & ((1 << MMCI_##name##_SIZE) - 1)) << MMCI_##name##_OFFSET) +#define MMCI_GETBF(name,value) (((value) >> MMCI_##name##_OFFSET) & ((1 << MMCI_##name##_SIZE) - 1)) +#define MMCI_INSBF(name,value,old) (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) << MMCI_##name##_OFFSET)) | MMCI_MKBF(name, value)) + +#define mmci_readl(port,reg) readl((port)->regs + MMCI_##reg) +#define mmci_writel(port,reg,value) writel((value), (port)->regs + MMCI_##reg) + +#endif /* __ASM_AVR32_PERIPH_MMCI_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/pio2.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pio2.h --- u-boot-1.1.4/cpu/at32ap7xxx/pio2.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pio2.h 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,172 @@ +/* + * Register definitions for PIO2 + * + * Parallel Input/Output 2 + */ +#ifndef __ASM_AVR32_PIO2_H__ +#define __ASM_AVR32_PIO2_H__ + +/* PIO2 register offsets */ +#define PIO2_PER 0x0000 +#define PIO2_PDR 0x0004 +#define PIO2_PSR 0x0008 +#define PIO2_OER 0x0010 +#define PIO2_ODR 0x0014 +#define PIO2_OSR 0x0018 +#define PIO2_IFER 0x0020 +#define PIO2_IFDR 0x0024 +#define PIO2_ISFR 0x0028 +#define PIO2_SODR 0x0030 +#define PIO2_CODR 0x0034 +#define PIO2_ODSR 0x0038 +#define PIO2_PDSR 0x003c +#define PIO2_IER 0x0040 +#define PIO2_IDR 0x0044 +#define PIO2_IMR 0x0048 +#define PIO2_ISR 0x004c +#define PIO2_MDER 0x0050 +#define PIO2_MDDR 0x0054 +#define PIO2_MDSR 0x0058 +#define PIO2_PUDR 0x0060 +#define PIO2_PUER 0x0064 +#define PIO2_PUSR 0x0068 +#define PIO2_ASR 0x0070 +#define PIO2_BSR 0x0074 +#define PIO2_ABSR 0x0078 +#define PIO2_OWER 0x00a0 +#define PIO2_OWDR 0x00a4 +#define PIO2_OWSR 0x00a8 + +/* Bitfields in PER */ + +/* Bitfields in PDR */ + +/* Bitfields in PSR */ + +/* Bitfields in OER */ + +/* Bitfields in ODR */ + +/* Bitfields in OSR */ + +/* Bitfields in IFER */ + +/* Bitfields in IFDR */ + +/* Bitfields in ISFR */ + +/* Bitfields in SODR */ + +/* Bitfields in CODR */ + +/* Bitfields in ODSR */ + +/* Bitfields in PDSR */ + +/* Bitfields in IER */ + +/* Bitfields in IDR */ + +/* Bitfields in IMR */ + +/* Bitfields in ISR */ + +/* Bitfields in MDER */ + +/* Bitfields in MDDR */ + +/* Bitfields in MDSR */ + +/* Bitfields in PUDR */ + +/* Bitfields in PUER */ + +/* Bitfields in PUSR */ + +/* Bitfields in ASR */ + +/* Bitfields in BSR */ + +/* Bitfields in ABSR */ +#define PIO2_P0_OFFSET 0 +#define PIO2_P0_SIZE 1 +#define PIO2_P1_OFFSET 1 +#define PIO2_P1_SIZE 1 +#define PIO2_P2_OFFSET 2 +#define PIO2_P2_SIZE 1 +#define PIO2_P3_OFFSET 3 +#define PIO2_P3_SIZE 1 +#define PIO2_P4_OFFSET 4 +#define PIO2_P4_SIZE 1 +#define PIO2_P5_OFFSET 5 +#define PIO2_P5_SIZE 1 +#define PIO2_P6_OFFSET 6 +#define PIO2_P6_SIZE 1 +#define PIO2_P7_OFFSET 7 +#define PIO2_P7_SIZE 1 +#define PIO2_P8_OFFSET 8 +#define PIO2_P8_SIZE 1 +#define PIO2_P9_OFFSET 9 +#define PIO2_P9_SIZE 1 +#define PIO2_P10_OFFSET 10 +#define PIO2_P10_SIZE 1 +#define PIO2_P11_OFFSET 11 +#define PIO2_P11_SIZE 1 +#define PIO2_P12_OFFSET 12 +#define PIO2_P12_SIZE 1 +#define PIO2_P13_OFFSET 13 +#define PIO2_P13_SIZE 1 +#define PIO2_P14_OFFSET 14 +#define PIO2_P14_SIZE 1 +#define PIO2_P15_OFFSET 15 +#define PIO2_P15_SIZE 1 +#define PIO2_P16_OFFSET 16 +#define PIO2_P16_SIZE 1 +#define PIO2_P17_OFFSET 17 +#define PIO2_P17_SIZE 1 +#define PIO2_P18_OFFSET 18 +#define PIO2_P18_SIZE 1 +#define PIO2_P19_OFFSET 19 +#define PIO2_P19_SIZE 1 +#define PIO2_P20_OFFSET 20 +#define PIO2_P20_SIZE 1 +#define PIO2_P21_OFFSET 21 +#define PIO2_P21_SIZE 1 +#define PIO2_P22_OFFSET 22 +#define PIO2_P22_SIZE 1 +#define PIO2_P23_OFFSET 23 +#define PIO2_P23_SIZE 1 +#define PIO2_P24_OFFSET 24 +#define PIO2_P24_SIZE 1 +#define PIO2_P25_OFFSET 25 +#define PIO2_P25_SIZE 1 +#define PIO2_P26_OFFSET 26 +#define PIO2_P26_SIZE 1 +#define PIO2_P27_OFFSET 27 +#define PIO2_P27_SIZE 1 +#define PIO2_P28_OFFSET 28 +#define PIO2_P28_SIZE 1 +#define PIO2_P29_OFFSET 29 +#define PIO2_P29_SIZE 1 +#define PIO2_P30_OFFSET 30 +#define PIO2_P30_SIZE 1 +#define PIO2_P31_OFFSET 31 +#define PIO2_P31_SIZE 1 + +/* Bitfields in OWER */ + +/* Bitfields in OWDR */ + +/* Bitfields in OWSR */ + +/* Bit manipulation macros */ +#define PIO2_BIT(name) (1 << PIO2_##name##_OFFSET) +#define PIO2_BF(name,value) (((value) & ((1 << PIO2_##name##_SIZE) - 1)) << PIO2_##name##_OFFSET) +#define PIO2_BFEXT(name,value) (((value) >> PIO2_##name##_OFFSET) & ((1 << PIO2_##name##_SIZE) - 1)) +#define PIO2_BFINS(name,value,old) (((old) & ~(((1 << PIO2_##name##_SIZE) - 1) << PIO2_##name##_OFFSET)) | PIO2_BF(name,value)) + +/* Register access macros */ +#define pio2_readl(port,reg) readl((port)->regs + PIO2_##reg) +#define pio2_writel(port,reg,value) writel((value), (port)->regs + PIO2_##reg) + +#endif /* __ASM_AVR32_PIO2_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/pio.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pio.c --- u-boot-1.1.4/cpu/at32ap7xxx/pio.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pio.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include + +#include "pio2.h" + +struct pio_state { + const struct device *dev; + u32 alloc_mask; +}; + +static struct pio_state pio_state[CFG_NR_PIOS]; + +int gpio_set_func(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins, enum gpio_func func) +{ + const struct device *gpio; + struct pio_state *state; + u32 mask; + + state = &pio_state[gpio_devid - DEVICE_PIOA]; + + gpio = get_device(gpio_devid); + if (!gpio) + return -EBUSY; + + state->dev = gpio; + mask = ((1 << nr_pins) - 1) << start; + + if (mask & state->alloc_mask) { + put_device(gpio); + return -EBUSY; + } + state->alloc_mask |= mask; + + switch (func) { + case GPIO_FUNC_GPIO: + /* TODO */ + return -EINVAL; + case GPIO_FUNC_A: + pio2_writel(gpio, ASR, mask); + pio2_writel(gpio, PDR, mask); + pio2_writel(gpio, PUDR, mask); + break; + case GPIO_FUNC_B: + pio2_writel(gpio, BSR, mask); + pio2_writel(gpio, PDR, mask); + pio2_writel(gpio, PUDR, mask); + break; + } + + return 0; +} + +void gpio_free(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins) +{ + const struct device *gpio; + struct pio_state *state; + u32 mask; + + state = &pio_state[gpio_devid - DEVICE_PIOA]; + gpio = state->dev; + mask = ((1 << nr_pins) - 1) << start; + + pio2_writel(gpio, ODR, mask); + pio2_writel(gpio, PER, mask); + + state->alloc_mask &= ~mask; + put_device(gpio); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/pm.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pm.c --- u-boot-1.1.4/cpu/at32ap7xxx/pm.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pm.c 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CFG_POWER_MANAGER +#include +#include + +#include +#include + +#include "sm.h" + +/* Sanity checks */ +#if (CFG_CLKDIV_CPU > CFG_CLKDIV_AHB) \ + || (CFG_CLKDIV_AHB > CFG_CLKDIV_APBA) \ + || (CFG_CLKDIV_AHB > CFG_CLKDIV_APBB) +# error Constraint fCPU >= fAHB >= fAPB{A,B} violated +#endif +#if (CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1) +# error Invalid PLL multiplier and/or divider +#endif + +struct clock_domain_state { + const struct device *bridge; + unsigned long freq; + u32 mask; +}; +static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS]; + +int pm_enable_clock(enum clock_domain_id id, unsigned int index) +{ + DECLARE_GLOBAL_DATA_PTR; + const struct clock_domain *ckd = &chip_clock[id]; + struct clock_domain_state *state = &ckd_state[id]; + + if (ckd->bridge != NO_DEVICE) { + state->bridge = get_device(ckd->bridge); + if (!state->bridge) + return -EBUSY; + } + + state->mask |= 1 << index; + if (gd->sm) + writel(state->mask, gd->sm->regs + ckd->reg); + + return 0; +} + +void pm_disable_clock(enum clock_domain_id id, unsigned int index) +{ + DECLARE_GLOBAL_DATA_PTR; + const struct clock_domain *ckd = &chip_clock[id]; + struct clock_domain_state *state = &ckd_state[id]; + + state->mask &= ~(1 << index); + if (gd->sm) + writel(state->mask, gd->sm->regs + ckd->reg); + + if (ckd->bridge) + put_device(state->bridge); +} + +unsigned long pm_get_clock_freq(enum clock_domain_id domain) +{ + return ckd_state[domain].freq; +} + +void pm_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + uint32_t cksel = 0; + unsigned long pll0_hz; + + /* Make sure we don't disable any device we're already using */ + get_device(DEVICE_HRAMC); + get_device(DEVICE_HEBI); + + /* Enable the PICO as well */ + ckd_state[CLOCK_CPU].mask |= 1; + + gd->sm = get_device(DEVICE_SM); + if (!gd->sm) + panic("Unable to claim system manager device!\n"); + + /* Disable any devices that haven't been explicitly claimed */ + sm_writel(gd->sm, PM_APBB_MASK, ckd_state[CLOCK_APBB].mask); + sm_writel(gd->sm, PM_APBA_MASK, ckd_state[CLOCK_APBA].mask); + sm_writel(gd->sm, PM_AHB_MASK, ckd_state[CLOCK_AHB].mask); + sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask); + + /* Initialize the PLL */ + pll0_hz = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL; + + sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) + | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) + | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) + | SM_BF(PLLOPT, CFG_PLL0_OPT) + | SM_BF(PLLOSC, 0) + | SM_BIT(PLLEN))); + + /* Wait for lock */ + while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ; + + /* Set up clocks for the CPU and all peripheral buses */ + if (CFG_CLKDIV_CPU) { + cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); + ckd_state[CLOCK_CPU].freq = pll0_hz / (1 << CFG_CLKDIV_CPU); + } else { + ckd_state[CLOCK_CPU].freq = pll0_hz; + } + if (CFG_CLKDIV_AHB) { + cksel |= SM_BIT(AHBDIV) | SM_BF(AHBSEL, CFG_CLKDIV_AHB - 1); + ckd_state[CLOCK_AHB].freq = pll0_hz / (1 << CFG_CLKDIV_AHB); + } else { + ckd_state[CLOCK_AHB].freq = pll0_hz; + } + if (CFG_CLKDIV_APBA) { + cksel |= SM_BIT(APBADIV) | SM_BF(APBASEL, CFG_CLKDIV_APBA - 1); + ckd_state[CLOCK_APBA].freq = pll0_hz / (1 << CFG_CLKDIV_APBA); + } else { + ckd_state[CLOCK_APBA].freq = pll0_hz; + } + if (CFG_CLKDIV_APBB) { + cksel |= SM_BIT(APBBDIV) | SM_BF(APBBSEL, CFG_CLKDIV_APBB - 1); + ckd_state[CLOCK_APBB].freq = pll0_hz / (1 << CFG_CLKDIV_APBB); + } else { + ckd_state[CLOCK_APBB].freq = pll0_hz; + } + sm_writel(gd->sm, PM_CKSEL, cksel); + + /* CFG_HZ currently depends on cpu_hz */ + gd->cpu_hz = ckd_state[CLOCK_CPU].freq; + + /* Use PLL0 as main clock */ + sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL)); +} + +#endif /* CFG_POWER_MANAGER */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/sm.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/sm.h --- u-boot-1.1.4/cpu/at32ap7xxx/sm.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/sm.h 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,240 @@ +/* + * Register definitions for SM + * + * System Manager + */ +#ifndef __ASM_AVR32_SM_H__ +#define __ASM_AVR32_SM_H__ + +/* SM register offsets */ +#define SM_PM_MCCTRL 0x0000 +#define SM_PM_CKSEL 0x0004 +#define SM_PM_CPU_MASK 0x0008 +#define SM_PM_AHB_MASK 0x000c +#define SM_PM_APBA_MASK 0x0010 +#define SM_PM_APBB_MASK 0x0014 +#define SM_PM_PLL0 0x0020 +#define SM_PM_PLL1 0x0024 +#define SM_PM_VCTRL 0x0030 +#define SM_PM_VMREF 0x0034 +#define SM_PM_VMV 0x0038 +#define SM_PM_IER 0x0040 +#define SM_PM_IDR 0x0044 +#define SM_PM_IMR 0x0048 +#define SM_PM_ISR 0x004c +#define SM_PM_ICR 0x0050 +#define SM_PM_GCCTRL 0x0060 +#define SM_RTC_CTRL 0x0080 +#define SM_RTC_VAL 0x0084 +#define SM_RTC_TOP 0x0088 +#define SM_RTC_IER 0x0090 +#define SM_RTC_IDR 0x0094 +#define SM_RTC_IMR 0x0098 +#define SM_RTC_ISR 0x009c +#define SM_RTC_ICR 0x00a0 +#define SM_WDT_CTRL 0x00b0 +#define SM_WDT_CLR 0x00b4 +#define SM_WDT_EXT 0x00b8 +#define SM_RC_RCAUSE 0x00c0 +#define SM_EIM_IER 0x0100 +#define SM_EIM_IDR 0x0104 +#define SM_EIM_IMR 0x0108 +#define SM_EIM_ISR 0x010c +#define SM_EIM_ICR 0x0110 +#define SM_EIM_MODE 0x0114 +#define SM_EIM_EDGE 0x0118 +#define SM_EIM_LEVEL 0x011c +#define SM_EIM_TEST 0x0120 +#define SM_EIM_NMIC 0x0124 + +/* Bitfields in PM_MCCTRL */ + +/* Bitfields in PM_CKSEL */ +#define SM_CPUSEL_OFFSET 0 +#define SM_CPUSEL_SIZE 3 +#define SM_CPUDIV_OFFSET 7 +#define SM_CPUDIV_SIZE 1 +#define SM_AHBSEL_OFFSET 8 +#define SM_AHBSEL_SIZE 3 +#define SM_AHBDIV_OFFSET 15 +#define SM_AHBDIV_SIZE 1 +#define SM_APBASEL_OFFSET 16 +#define SM_APBASEL_SIZE 3 +#define SM_APBADIV_OFFSET 23 +#define SM_APBADIV_SIZE 1 +#define SM_APBBSEL_OFFSET 24 +#define SM_APBBSEL_SIZE 3 +#define SM_APBBDIV_OFFSET 31 +#define SM_APBBDIV_SIZE 1 + +/* Bitfields in PM_CPU_MASK */ + +/* Bitfields in PM_AHB_MASK */ + +/* Bitfields in PM_APBA_MASK */ + +/* Bitfields in PM_APBB_MASK */ + +/* Bitfields in PM_PLL0 */ +#define SM_PLLEN_OFFSET 0 +#define SM_PLLEN_SIZE 1 +#define SM_PLLOSC_OFFSET 1 +#define SM_PLLOSC_SIZE 1 +#define SM_PLLOPT_OFFSET 2 +#define SM_PLLOPT_SIZE 3 +#define SM_PLLDIV_OFFSET 8 +#define SM_PLLDIV_SIZE 8 +#define SM_PLLMUL_OFFSET 16 +#define SM_PLLMUL_SIZE 8 +#define SM_PLLCOUNT_OFFSET 24 +#define SM_PLLCOUNT_SIZE 6 +#define SM_PLLTEST_OFFSET 31 +#define SM_PLLTEST_SIZE 1 + +/* Bitfields in PM_PLL1 */ + +/* Bitfields in PM_VCTRL */ +#define SM_VAUTO_OFFSET 0 +#define SM_VAUTO_SIZE 1 +#define SM_PM_VCTRL_VAL_OFFSET 8 +#define SM_PM_VCTRL_VAL_SIZE 7 + +/* Bitfields in PM_VMREF */ +#define SM_REFSEL_OFFSET 0 +#define SM_REFSEL_SIZE 4 + +/* Bitfields in PM_VMV */ +#define SM_PM_VMV_VAL_OFFSET 0 +#define SM_PM_VMV_VAL_SIZE 8 + +/* Bitfields in PM_IER */ + +/* Bitfields in PM_IDR */ + +/* Bitfields in PM_IMR */ + +/* Bitfields in PM_ISR */ + +/* Bitfields in PM_ICR */ +#define SM_LOCK0_OFFSET 0 +#define SM_LOCK0_SIZE 1 +#define SM_LOCK1_OFFSET 1 +#define SM_LOCK1_SIZE 1 +#define SM_WAKE_OFFSET 2 +#define SM_WAKE_SIZE 1 +#define SM_VOK_OFFSET 3 +#define SM_VOK_SIZE 1 +#define SM_VMRDY_OFFSET 4 +#define SM_VMRDY_SIZE 1 +#define SM_CKRDY_OFFSET 5 +#define SM_CKRDY_SIZE 1 + +/* Bitfields in PM_GCCTRL */ +#define SM_OSCSEL_OFFSET 0 +#define SM_OSCSEL_SIZE 1 +#define SM_PLLSEL_OFFSET 1 +#define SM_PLLSEL_SIZE 1 +#define SM_CEN_OFFSET 2 +#define SM_CEN_SIZE 1 +#define SM_CPC_OFFSET 3 +#define SM_CPC_SIZE 1 +#define SM_DIVEN_OFFSET 4 +#define SM_DIVEN_SIZE 1 +#define SM_DIV_OFFSET 8 +#define SM_DIV_SIZE 8 + +/* Bitfields in RTC_CTRL */ +#define SM_PCLR_OFFSET 1 +#define SM_PCLR_SIZE 1 +#define SM_TOPEN_OFFSET 2 +#define SM_TOPEN_SIZE 1 +#define SM_CLKEN_OFFSET 3 +#define SM_CLKEN_SIZE 1 +#define SM_PSEL_OFFSET 8 +#define SM_PSEL_SIZE 16 + +/* Bitfields in RTC_VAL */ +#define SM_RTC_VAL_VAL_OFFSET 0 +#define SM_RTC_VAL_VAL_SIZE 31 + +/* Bitfields in RTC_TOP */ +#define SM_RTC_TOP_VAL_OFFSET 0 +#define SM_RTC_TOP_VAL_SIZE 32 + +/* Bitfields in RTC_IER */ + +/* Bitfields in RTC_IDR */ + +/* Bitfields in RTC_IMR */ + +/* Bitfields in RTC_ISR */ + +/* Bitfields in RTC_ICR */ +#define SM_TOPI_OFFSET 0 +#define SM_TOPI_SIZE 1 + +/* Bitfields in WDT_CTRL */ +#define SM_KEY_OFFSET 24 +#define SM_KEY_SIZE 8 + +/* Bitfields in WDT_CLR */ + +/* Bitfields in WDT_EXT */ + +/* Bitfields in RC_RCAUSE */ +#define SM_POR_OFFSET 0 +#define SM_POR_SIZE 1 +#define SM_BOD_OFFSET 1 +#define SM_BOD_SIZE 1 +#define SM_EXT_OFFSET 2 +#define SM_EXT_SIZE 1 +#define SM_WDT_OFFSET 3 +#define SM_WDT_SIZE 1 +#define SM_NTAE_OFFSET 4 +#define SM_NTAE_SIZE 1 +#define SM_SERP_OFFSET 5 +#define SM_SERP_SIZE 1 + +/* Bitfields in EIM_IER */ + +/* Bitfields in EIM_IDR */ + +/* Bitfields in EIM_IMR */ + +/* Bitfields in EIM_ISR */ + +/* Bitfields in EIM_ICR */ + +/* Bitfields in EIM_MODE */ + +/* Bitfields in EIM_EDGE */ +#define SM_INT0_OFFSET 0 +#define SM_INT0_SIZE 1 +#define SM_INT1_OFFSET 1 +#define SM_INT1_SIZE 1 +#define SM_INT2_OFFSET 2 +#define SM_INT2_SIZE 1 +#define SM_INT3_OFFSET 3 +#define SM_INT3_SIZE 1 + +/* Bitfields in EIM_LEVEL */ + +/* Bitfields in EIM_TEST */ +#define SM_TESTEN_OFFSET 31 +#define SM_TESTEN_SIZE 1 + +/* Bitfields in EIM_NMIC */ +#define SM_EN_OFFSET 0 +#define SM_EN_SIZE 1 + +/* Bit manipulation macros */ +#define SM_BIT(name) (1 << SM_##name##_OFFSET) +#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET) +#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1)) +#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value)) + +/* Register access macros */ +#define sm_readl(port,reg) readl((port)->regs + SM_##reg) +#define sm_writel(port,reg,value) writel((value), (port)->regs + SM_##reg) + +#endif /* __ASM_AVR32_SM_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/start.S u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/start.S --- u-boot-1.1.4/cpu/at32ap7xxx/start.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/start.S 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include + +#ifndef PART_SPECIFIC_BOOTSTRAP +# define PART_SPECIFIC_BOOTSTRAP +#endif + +#define SYSREG_MMUCR_I_OFFSET 2 +#define SYSREG_MMUCR_S_OFFSET 4 + +#define SR_INIT (SYSREG_BIT(SR_GM) /* | SYSREG_BIT(SR_EM) */ | SYSREG_BIT(SR_M0)) +#define CPUCR_INIT (SYSREG_BIT(CPUCR_BI) | SYSREG_BIT(CPUCR_BE) \ + | SYSREG_BIT(CPUCR_FE) | SYSREG_BIT(CPUCR_RE) \ + | SYSREG_BIT(CPUCR_IBE) | SYSREG_BIT(CPUCR_IEE)) + + .text + .global _start +_start: + PART_SPECIFIC_BOOTSTRAP + + /* Reset the Status Register */ + mov r0, lo(SR_INIT) + orh r0, hi(SR_INIT) + mtsr SYSREG_SR, r0 + + /* Reset CPUCR and invalidate the BTB */ + mov r2, CPUCR_INIT + mtsr SYSREG_CPUCR, r2 + + /* Flush the caches */ + mov r1, 0 + cache r1[4], 8 + cache r1[0], 0 + sync 0 + + /* Reset the MMU to default settings */ + mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I) + mtsr SYSREG_MMUCR, r0 + + /* Internal RAM should not need any initialization. We might + have to initialize external RAM here if the part doesn't + have internal RAM (or we may use the data cache) */ + + /* Jump to cacheable segment */ + lddpc pc, 1f + + .align 2 +1: .long 2f + +2: lddpc sp, sp_init + + /* + * Relocate the data section and initialize .bss. Everything + * is guaranteed to be at least doubleword aligned by the + * linker script. + */ + lddpc r12, .Ldata_vma + lddpc r11, .Ldata_lma + lddpc r10, .Ldata_end + sub r10, r12 +4: ld.d r8, r11++ + sub r10, 8 + st.d r12++, r8 + brne 4b + + mov r8, 0 + mov r9, 0 + lddpc r10, .Lbss_end + sub r10, r12 +4: sub r10, 8 + st.d r12++, r8 + brne 4b + + /* Initialize the GOT pointer */ + lddpc r6, got_init +3: rsub r6, pc + ld.w pc, r6[start_u_boot@got] + + .align 2 + .type sp_init,@object +sp_init: + .long CFG_INIT_SP_ADDR +got_init: + .long 3b - _GLOBAL_OFFSET_TABLE_ +.Ldata_lma: + .long __data_lma +.Ldata_vma: + .long _data +.Ldata_end: + .long _edata +.Lbss_end: + .long _end diff -Nur u-boot-1.1.4/disk/part.c u-boot-1.1.4-avr32-20060621/disk/part.c --- u-boot-1.1.4/disk/part.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/disk/part.c 2006-06-21 11:58:26.000000000 +0200 @@ -126,6 +126,7 @@ #if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ (CONFIG_COMMANDS & CFG_CMD_USB) || \ + (CONFIG_COMMANDS & CFG_CMD_MMC) || \ defined(CONFIG_SYSTEMACE) ) #if defined(CONFIG_MAC_PARTITION) || \ diff -Nur u-boot-1.1.4/drivers/atmel_usart.c u-boot-1.1.4-avr32-20060621/drivers/atmel_usart.c --- u-boot-1.1.4/drivers/atmel_usart.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/drivers/atmel_usart.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include + +#ifdef CONFIG_USART3_SERIAL +#include +#include + +#include "atmel_usart.h" + +#define USART_MODE_NORMAL 0 +#define USART_CLKS_MCK 0 +#define USART_CHRL_8BITS 3 +#define USART_PAR_NONE 4 +#define USART_NBSTOP_1BIT 0 + +void serial_setbrg(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long divisor; + unsigned long usart_hz; + + /* + * Master Clock + * Baud Rate = -------------- + * 16 * CD + */ + usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id); + divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; + usart3_writel(gd->console_uart, US_BRGR, + USART3_MKBF(US_BRGR_CD, divisor)); +} + +int serial_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + usart3_writel(gd->console_uart, US_CR, + USART3_BIT(US_CR_RSTRX) | USART3_BIT(US_CR_RSTTX)); + + serial_setbrg(); + + usart3_writel(gd->console_uart, US_CR, + USART3_BIT(US_CR_RXEN) | USART3_BIT(US_CR_TXEN)); + usart3_writel(gd->console_uart, US_MR, + USART3_MKBF(US_MR_USART_MODE, USART_MODE_NORMAL) + | USART3_MKBF(US_MR_USCLKS, USART_CLKS_MCK) + | USART3_MKBF(US_MR_CHRL, USART_CHRL_8BITS) + | USART3_MKBF(US_MR_PAR, USART_PAR_NONE) + | USART3_MKBF(US_MR_NBSTOP, USART_NBSTOP_1BIT)); + + return 0; +} + +void serial_putc(char c) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (c == '\n') + serial_putc('\r'); + + while (!(usart3_readl(gd->console_uart, US_CSR) + & USART3_BIT(US_CSR_TXRDY))) ; + usart3_writel(gd->console_uart, US_THR, c); +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +int serial_getc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + while (!(usart3_readl(gd->console_uart, US_CSR) + & USART3_BIT(US_CSR_RXRDY))) ; + return usart3_readl(gd->console_uart, US_RHR); +} + +int serial_tstc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + return (usart3_readl(gd->console_uart, US_CSR) + & USART3_BIT(US_CSR_RXRDY)) != 0; +} + +#endif /* CONFIG_USART3_SERIAL */ diff -Nur u-boot-1.1.4/drivers/atmel_usart.h u-boot-1.1.4-avr32-20060621/drivers/atmel_usart.h --- u-boot-1.1.4/drivers/atmel_usart.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/drivers/atmel_usart.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PERIPH_USART3_H__ +#define __ASM_AVR32_PERIPH_USART3_H__ + +#define USART3_US_BRGR 0x0020 +# define USART3_US_BRGR_CD_OFFSET 0 +# define USART3_US_BRGR_CD_SIZE 16 +#define USART3_US_CR 0x0000 +# define USART3_US_CR_COMM_RX_OFFSET 31 +# define USART3_US_CR_COMM_RX_SIZE 1 +# define USART3_US_CR_COMM_TX_OFFSET 30 +# define USART3_US_CR_COMM_TX_SIZE 1 +# define USART3_US_CR_DTRDIS_OFFSET 17 +# define USART3_US_CR_DTRDIS_SIZE 1 +# define USART3_US_CR_DTREN_OFFSET 16 +# define USART3_US_CR_DTREN_SIZE 1 +# define USART3_US_CR_RETTO_OFFSET 15 +# define USART3_US_CR_RETTO_SIZE 1 +# define USART3_US_CR_RSTIT_OFFSET 13 +# define USART3_US_CR_RSTIT_SIZE 1 +# define USART3_US_CR_RSTNACK_OFFSET 14 +# define USART3_US_CR_RSTNACK_SIZE 1 +# define USART3_US_CR_RSTRX_OFFSET 2 +# define USART3_US_CR_RSTRX_SIZE 1 +# define USART3_US_CR_RSTSTA_OFFSET 8 +# define USART3_US_CR_RSTSTA_SIZE 1 +# define USART3_US_CR_RSTTX_OFFSET 3 +# define USART3_US_CR_RSTTX_SIZE 1 +# define USART3_US_CR_RTSDIS_OFFSET 19 +# define USART3_US_CR_RTSDIS_SIZE 1 +# define USART3_US_CR_RTSEN_OFFSET 18 +# define USART3_US_CR_RTSEN_SIZE 1 +# define USART3_US_CR_RXDIS_OFFSET 5 +# define USART3_US_CR_RXDIS_SIZE 1 +# define USART3_US_CR_RXEN_OFFSET 4 +# define USART3_US_CR_RXEN_SIZE 1 +# define USART3_US_CR_SENDA_OFFSET 12 +# define USART3_US_CR_SENDA_SIZE 1 +# define USART3_US_CR_STPBRK_OFFSET 10 +# define USART3_US_CR_STPBRK_SIZE 1 +# define USART3_US_CR_STTBRK_OFFSET 9 +# define USART3_US_CR_STTBRK_SIZE 1 +# define USART3_US_CR_STTTO_OFFSET 11 +# define USART3_US_CR_STTTO_SIZE 1 +# define USART3_US_CR_TXDIS_OFFSET 7 +# define USART3_US_CR_TXDIS_SIZE 1 +# define USART3_US_CR_TXEN_OFFSET 6 +# define USART3_US_CR_TXEN_SIZE 1 +#define USART3_US_CSR 0x0014 +# define USART3_US_CSR_COMM_RX_OFFSET 31 +# define USART3_US_CSR_COMM_RX_SIZE 1 +# define USART3_US_CSR_COMM_TX_OFFSET 30 +# define USART3_US_CSR_COMM_TX_SIZE 1 +# define USART3_US_CSR_CTS_OFFSET 23 +# define USART3_US_CSR_CTS_SIZE 1 +# define USART3_US_CSR_CTSIC_OFFSET 19 +# define USART3_US_CSR_CTSIC_SIZE 1 +# define USART3_US_CSR_DCD_OFFSET 22 +# define USART3_US_CSR_DCD_SIZE 1 +# define USART3_US_CSR_DCDIC_OFFSET 18 +# define USART3_US_CSR_DCDIC_SIZE 1 +# define USART3_US_CSR_DSR_OFFSET 21 +# define USART3_US_CSR_DSR_SIZE 1 +# define USART3_US_CSR_DSRIC_OFFSET 17 +# define USART3_US_CSR_DSRIC_SIZE 1 +# define USART3_US_CSR_ENDRX_OFFSET 3 +# define USART3_US_CSR_ENDRX_SIZE 1 +# define USART3_US_CSR_ENDTX_OFFSET 4 +# define USART3_US_CSR_ENDTX_SIZE 1 +# define USART3_US_CSR_FRAME_OFFSET 6 +# define USART3_US_CSR_FRAME_SIZE 1 +# define USART3_US_CSR_ITERATION_OFFSET 10 +# define USART3_US_CSR_ITERATION_SIZE 1 +# define USART3_US_CSR_NACK_OFFSET 13 +# define USART3_US_CSR_NACK_SIZE 1 +# define USART3_US_CSR_OVRE_OFFSET 5 +# define USART3_US_CSR_OVRE_SIZE 1 +# define USART3_US_CSR_PARE_OFFSET 7 +# define USART3_US_CSR_PARE_SIZE 1 +# define USART3_US_CSR_RI_OFFSET 20 +# define USART3_US_CSR_RI_SIZE 1 +# define USART3_US_CSR_RIIC_OFFSET 16 +# define USART3_US_CSR_RIIC_SIZE 1 +# define USART3_US_CSR_RXBRK_OFFSET 2 +# define USART3_US_CSR_RXBRK_SIZE 1 +# define USART3_US_CSR_RXBUFF_OFFSET 12 +# define USART3_US_CSR_RXBUFF_SIZE 1 +# define USART3_US_CSR_RXRDY_OFFSET 0 +# define USART3_US_CSR_RXRDY_SIZE 1 +# define USART3_US_CSR_TIMEOUT_OFFSET 8 +# define USART3_US_CSR_TIMEOUT_SIZE 1 +# define USART3_US_CSR_TXBUFE_OFFSET 11 +# define USART3_US_CSR_TXBUFE_SIZE 1 +# define USART3_US_CSR_TXEMPTY_OFFSET 9 +# define USART3_US_CSR_TXEMPTY_SIZE 1 +# define USART3_US_CSR_TXRDY_OFFSET 1 +# define USART3_US_CSR_TXRDY_SIZE 1 +#define USART3_US_FIDI 0x0040 +# define USART3_US_FIDI_FI_DI_RATIO_OFFSET 0 +# define USART3_US_FIDI_FI_DI_RATIO_SIZE 11 +#define USART3_US_IDR 0x000C +# define USART3_US_IDR_COMM_RX_OFFSET 31 +# define USART3_US_IDR_COMM_RX_SIZE 1 +# define USART3_US_IDR_COMM_TX_OFFSET 30 +# define USART3_US_IDR_COMM_TX_SIZE 1 +# define USART3_US_IDR_CTSIC_OFFSET 19 +# define USART3_US_IDR_CTSIC_SIZE 1 +# define USART3_US_IDR_DCDIC_OFFSET 18 +# define USART3_US_IDR_DCDIC_SIZE 1 +# define USART3_US_IDR_DSRIC_OFFSET 17 +# define USART3_US_IDR_DSRIC_SIZE 1 +# define USART3_